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data sheet, v3.3, feb. 2005 microcontrollers never stop thinking. c167cr c167sr 16-bit single-chip microcontroller
edition 2005-02 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warrant ies, including but not limited to warran ties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms an d conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or system s with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v3.3, feb. 2005 microcontrollers never stop thinking. c167cr c167sr 16-bit single-chip microcontroller
template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15 c167cr, c167sr revision history: 2005-02 v3.3 previous version: v3.2, 2001-07 v3.1, 2000-04 v3.0, 2000-02 1999-10 (introduction of clock-related timing) 1999-06 1999-03 (summarizes and replaces all older docs) 1998-03 (c167sr/cr , 25 mhz addendum) 07.97 / 12.96 (c167cr-4rm) 12.96 (c167cr-16rm) 06.95 (c167cr, c167sr) 06.94 / 05.93 (c167) page subjects (major changes since last revision) all the layout of several graphics and text structur es has been adapted to company documentation rules, obvious typographical errors have been corrected. all the contents of th is document have been re -arranged into numbered sections and a table of contents has been added. 6 bga-type added to product list 8 pin designation corrected (pin 78) 9 input threshold contro l added to port 6 17 25 pin diagram and pin descrip tion for bga package added 45 port 6 added to input-th reshold controlled ports 85 mechanical package drawi ng corrected (p-mqfp-144-8) 86 mechanical package draw ing added (p-bga-176-2) we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
c167cr c167sr table of contents data sheet 3 v3.3, 2005-02 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin configuration and definition for p-mqfp-1 44-8 . . . . . . . . . . . . . . . . . . 8 2.3 pin configuration and definition for p-bga- 176-2 . . . . . . . . . . . . . . . . . . 17 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.5 capture/compare (capcom) units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6 pwm module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.7 general purpose timer (g pt) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.8 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.9 serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.10 can-module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.11 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.12 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.13 oscillator watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.14 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.15 special function registers over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3 analog/digital converter parame ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.1 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.2 external clock drive xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4.3 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.4.4 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table of contents
c167cr/c167sr 16-bit single-chip microcontroller c166 family data sheet 4 v3.3, 2005-02 1 summary of features ? high performance 16-bit cpu with 4-stage pipeline ? 80/60 ns instruction cycle time at 25/33 mhz cpu clock ? 400/303 ns multiplication (16 16 bits), 800/606 ns di vision (32 / 16 bits) ? enhanced boolean bit manipulation facilities ? additional instructions to su pport hll and operating systems ? register-based design with mult iple variable register banks ? single-cycle contex t switching support ? 16 mbytes total linear addr ess space for code and data ? 1024 bytes on-chip specia l function register area ? 16-priority-level interrupt system with 56 sources, sa mple-rate down to 40/30 ns ? 8-channel interrupt -driven single-cycle data transfer facilities via peripheral event controller (pec) ? clock generation via on-chip pll (factors 1:1.5/2/2.5/3/4/5), via prescaler or vi a direct clock input ? on-chip memory modules ? 2 kbytes on-chip internal ram (iram) ? 2 kbytes on-chip extension ram (xram) ? 128/32 kbytes on-chip mask rom ? on-chip peripheral modules ? 16-channel 10-bit a/d converter with programmable conversion time down to 7.8 s ? two 16-channel capture/compare units ? 4-channel pwm unit ? two multi-functional general pu rpose timer units with 5 timers ? two serial channels (syn chronous/asynchronous and high-speed-synchronous) ? on-chip can interface (rev. 2.0b active) with 15 message objects (full can / basic can) ? up to 16 mbytes external address space fo r code and data ? programmable external bus characte ristics for differ ent address ranges ? multiplexed or demultiplexed external ad dress/data buses with 8-bit or 16-bit data bus width ? five programmable ch ip-select signals ? hold- and hold-acknowledg e bus arbitration support ? idle and power down modes ? programmable watchdog time r and oscillator watchdog
c167cr c167sr summary of features data sheet 5 v3.3, 2005-02 ? up to 111 general purpose i/o lines, partly with selectable input thresholds and hysteresis ? supported by a large range of deve lopment tools like c-compilers, macro-assembler packages, emulators, evaluation boar ds, hll-debuggers, simulators, logic an alyzer disassemblers, programming boards ? on-chip bootstrap loader ? 144-pin mqfp package ? 176-pin bga package 1) ordering information the ordering code for infineon microcontrol lers provides an exact reference to the required product. this or dering code identifies: ? the derivative itself, i.e. it s function set, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes for the c167cr please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. note: the ordering codes for mask-rom vers ions are defined fo r each product after verification of the respective rom code. this document describes several derivatives of the c167 group. table 1 enumerates these derivatives and summarizes the differences . as this document re fers to all of these derivatives, some descriptions may not apply to a sp ecific product. for simplicity all versions are referred to by the term c167cr throughout this document. 1) the external connections of the c1 67cr in p-bga-176-2 are referred to as pins throughout this document, although they are mechanically realized as solder balls.
c167cr c167sr summary of features data sheet 6 v3.3, 2005-02 table 1 c167cr derivative synopsis derivative 1) program rom size xram size operating frequency package sak-c167sr-lm sab-c167sr-lm ? 2 kbytes 25 mhz p-mqfp-144-8 sak-c167sr-l33m sab-c167sr-l33m ? 2 kbytes 33 mhz p-mqfp-144-8 sak-c167cr-lm saf-c167cr-lm sab-c167cr-lm ? 2 kbytes 25 mhz p-mqfp-144-8 sak-c167cr-l33m sab-c167cr-l33m ? 2 kbytes 33 mhz p-mqfp-144-8 sak-c167cr-4rm sab-c167cr-4rm 32 kbytes 2 kbytes 25 mhz p-mqfp-144-8 sak-c167cr-4r33m sab-c167cr-4r33m 32 kbytes 2 kbytes 33 mhz p-mqfp-144-8 sak-c167cr-16rm 128 kbytes 2 kbytes 25 mhz p-mqfp-144-8 sak-c167cr-16r33m 1 28 kbytes 2 kbytes 33 mhz p-mqfp-144-8 sak-c167cr-le ? 2 kbytes 25 mhz p-bga-176-2 1) this data sheet is valid for devices manufactured in 0.5 m technology, i.e. devices starting with and including design step ga(-t)6.
c167cr c167sr general device information data sheet 7 v3.3, 2005-02 2 general device information 2.1 introduction the c167cr derivatives are high performanc e derivatives of th e infineon c166 family of full featured single-c hip cmos microcontrollers. they combine high cpu performance (up to 16.5 million instructions pe r second) with high pe ripheral functionality and enhanced io-capabilities. they also provide clock gen eration via pll and various on-chip memory modules such as program rom, internal ram, and extension ram. figure 1 logic symbol mcl04411 xtal1 xtal2 rstout ale nmi rd rstin port 0 16 bit 16 bit port 1 16 bit port 2 15 bit port 3 8 bit port 4 v aref agnd v wr/wrl port 5 16 bit port 6 8 bit ea ready port 7 8 bit 8 bit port 8 dd v ss v c167cr
c167cr c167sr general device information data sheet 8 v3.3, 2005-02 2.2 pin configuration and de finition for p-mqfp-144-8 the pins of the c167cr ar e described in detail in table 2 , including all their alternate functions. figure 2 summarizes all pins in a condens ed way, showing their location on the 4 sides of the package. note: the p-bga-176-2 is described in table 3 and figure 3 . figure 2 pin configuration p-mqfp-144-8 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 v aref v agnd p5.10/an10/t6eud p5.11/an11/t5eud p5.12/an12/t6in p5.13/an13/t5in p5.14/an14/t4eud p5.15/an15/t2eud v ss v dd p2.0/cc0io p2.1/cc1io p2.2/cc2io p2.3/cc3io p2.4/cc4io p2.5/cc5io p2.6/cc6io p2.7/cc7io v ss v dd p2.8/cc8io/ex0in p2.9/cc9io/ex1in p2.10/cc10io/ex2in p2.11/cc11io/ex3in p2.12/cc12io/ex4in p2.13/cc13io/ex5in p2.14/cc14io/ex6in p2.15/cc15io/ex7in/t7in p3.0/t0in p3.1/t6out p3.2/capin p3.3/t3out p3.4/t3eud p3.5/t4in v ss v dd v dd v ss nmi rstout rstin v ss xtal1 xtal2 v dd p1h.7/a15/cc27io p1h.6/a14/cc26io p1h.5/a13/cc25io p1h.4/a12/cc24io p1h.3/a11 p1h.2/a10 p1h.1/a9 p1h.0/a8 v ss v dd p1l.7/a7 p1l.6/a6 p1l.5/a5 p1l.4/a4 p1l.3/a3 p1l.2/a2 p1l.1/a1 p1l.0/a0 p0h.7/ad15 p0h.6/ad14 p0h.5/ad13 p0h.4/ad12 p0h.3/ad11 p0h.2/ad10 p0h.1/ad9 v ss v dd p0h.0/ad8 p0l.7/ad7 p0l.6/ad6 p0l.5/ad5 p0l.4/ad4 p0l.3/ad3 p0l.2/ad2 p0l.1/ad1 p0l.0/ad0 ea ale ready wr/wrl rd v ss v dd p4.7/a23 p4.6/a22/can1_txd p4.5/a21/can1_rxd p4.4/a20 p4.3/a19 p4.2/a18 p4.1/a17 p4.0/a16 owe v ss v dd p3.15/clkout p3.13/sclk p3.12/bhe/wrh p3.11/rxd0 p3.10/txd0 p3.9/mtsr p3.8/mrst p3.7/t2in p3.6/t3in p6.0/cs0 p6.1/cs1 p6.2/cs2 p6.3/cs3 p6.4/cs4 p6.5/hold p6.6/hlda p6.7/breq p8.0/cc16io p8.1/cc17io p8.2/cc18io p8.3/cc19io p8.4/cc20io p8.5/cc21io p8.6/cc22io p8.7/cc23io v dd v ss p7.0/pout0 p7.1/pout1 p7.2/pout2 p7.3/pout3 p7.4/cc28io p7.5/cc29io p7.6/cc30io p7.7/cc31io p5.0/an0 p5.1/an1 p5.2/an2 p5.3/an3 p5.4/an4 p5.5/an5 p5.6/an6 p5.7/an7 p5.8/an8 p5.9/an9 c167cr mcp04410
c167cr c167sr general device information data sheet 9 v3.3, 2005-02 table 2 pin definitions an d functions p-mqfp-144-8 symbol pin no. input outp. function p6 p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 1 2 3 4 5 6 7 8 io o o o o o i i/o o port 6 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 6 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 6 is selectable (ttl or special). the port 6 pins also serv e for alternate functions: cs0 chip select 0 output cs1 chip select 1 output cs2 chip select 2 output cs3 chip select 3 output cs4 chip select 4 output hold external master hold request input hlda hold acknowledge output (master mode) or input (slave mode) breq bus request output p8 p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 9 10 11 12 13 14 15 16 io i/o i/o i/o i/o i/o i/o i/o i/o port 8 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 8 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 8 is selectable (ttl or special). the following port 8 pins also serve for alternate functions: cc16io capcom2: cc16 capt ure inp./compare outp. cc17io capcom2: cc17 capt ure inp./compare outp. cc18io capcom2: cc18 capt ure inp./compare outp. cc19io capcom2: cc19 capt ure inp./compare outp. cc20io capcom2: cc20 capt ure inp./compare outp. cc21io capcom2: cc21 capt ure inp./compare outp. cc22io capcom2: cc22 capt ure inp./compare outp. cc23io capcom2: cc23 capt ure inp./compare outp.
c167cr c167sr general device information data sheet 10 v3.3, 2005-02 p7 p7.0 p7.1 p7.2 p7.3 p7.4 p7.5 p7.6 p7.7 19 20 21 22 23 24 25 26 io o o o o i/o i/o i/o i/o port 7 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 7 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 7 is selectable (ttl or special). the following port 7 pins also serve for alternate functions: pout0 pwm channel 0 output pout1 pwm channel 1 output pout2 pwm channel 2 output pout3 pwm channel 3 output cc28io capcom2: cc28 capt ure inp./compare outp. cc29io capcom2: cc29 capt ure inp./compare outp. cc30io capcom2: cc30 capt ure inp./compare outp. cc31io capcom2: cc31 capt ure inp./compare outp. p5 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 p5.8 p5.9 p5.10 p5.11 p5.12 p5.13 p5.14 p5.15 27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44 i i i i i i i i i i i i i i i i i port 5 is a 16-bit input-only port with schmitt-trigger characteristic. the pins of port 5 also serve as analog input c hannels for the a/d converter, or they serve as timer inputs: an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10, t6eud gpt2 timer t6 ext. up/down ctrl. inp. an11, t5eud gpt2 timer t5 ext. up/down ctrl. inp. an12, t6in gpt2 timer t6 count inp. an13, t5in gpt2 timer t5 count inp. an14, t4eud gpt1 timer t4 ext. up/down ctrl. inp. an15, t2eud gpt1 timer t5 ext. up/down ctrl. inp. table 2 pin definitions an d functions p-mqfp-144-8 (cont?d) symbol pin no. input outp. function
c167cr c167sr general device information data sheet 11 v3.3, 2005-02 p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 io i/o i/o i/o i/o i/o i/o i/o i/o i/o i i/o i i/o i i/o i i/o i i/o i i/o i i/o i i port 2 is a 16-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 2 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 2 is selectable (ttl or special). the following port 2 pins also serve for alternate functions: cc0io capcom1: cc0 captur e inp./compare output cc1io capcom1: cc1 captur e inp./compare output cc2io capcom1: cc2 captur e inp./compare output cc3io capcom1: cc3 captur e inp./compare output cc4io capcom1: cc4 captur e inp./compare output cc5io capcom1: cc5 captur e inp./compare output cc6io capcom1: cc6 captur e inp./compare output cc7io capcom1: cc7 captur e inp./compare output cc8io capcom1: cc8 captur e inp./compare output, ex0in fast external interrupt 0 input cc9io capcom1: cc9 captur e inp./compare output, ex1in fast external interrupt 1 input cc10io capcom1: cc10 capt ure inp./compare outp., ex2in fast external interrupt 2 input cc11io capcom1: cc11 capt ure inp./compare outp., ex3in fast external interrupt 3 input cc12io capcom1: cc12 capt ure inp./compare outp., ex4in fast external interrupt 4 input cc13io capcom1: cc13 capt ure inp./compare outp., ex5in fast external interrupt 5 input cc14io capcom1: cc14 capt ure inp./compare outp., ex6in fast external interrupt 6 input cc15io capcom1: cc15 capt ure inp./compare outp., ex7in fast external interrupt 7 input, t7in capcom2: timer t7 count input table 2 pin definitions an d functions p-mqfp-144-8 (cont?d) symbol pin no. input outp. function
c167cr c167sr general device information data sheet 12 v3.3, 2005-02 p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.15 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 io i o i o i i i i i/o i/o o i/o o o i/o o port 3 is a 15-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 3 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 3 is selectable (ttl or special). the following port 3 pins also serve for alternate functions: t0in capcom1 timer t0 count input t6out gpt2 timer t6 toggle latch output capin gpt2 register caprel capture input t3out gpt1 timer t3 toggle latch output t3eud gpt1 timer t3 extern al up/down control input t4in gpt1 timer t4 count/gate/reload/capture inp. t3in gpt1 timer t3 count/gate input t2in gpt1 timer t2 count/gate/reload/capture inp. mrst ssc master-receive/slave-transmit inp./outp. mtsr ssc master-transmit/slave-receive outp./inp. txd0 asc0 clock/data output (async./sync.) rxd0 asc0 data input (async .) or inp./outp. (sync.) bhe external memory high byte enab le signal, wrh external memory high byte write strobe sclk ssc master clock out put / slave clock input. clkout system clock ou tput (= cpu clock) owe ( v pp ) 84 i oscillator watchdog e nable. this input enab les the oscillator watchdog when high or disables it when low e.g. for testing purposes. an internal pull-up devi ce holds this input high if nothing is driving it. for normal operation pin owe should be high or not connected. in order to drive pin owe low draw a current of at least 200 a. table 2 pin definitions an d functions p-mqfp-144-8 (cont?d) symbol pin no. input outp. function
c167cr c167sr general device information data sheet 13 v3.3, 2005-02 p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 85 86 87 88 89 90 91 92 io o o o o o o i o o o port 4 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 4 can be used to output the segment address lines and for serial bus interfaces: a16 least significant segment address line a17 segment address line a18 segment address line a19 segment address line a20 segment address line a21 segment address line, can1_rxd can 1 receive data input a22 segment address line, can1_txd can 1 transmit data output a23 most significant segment address line rd 95 o external memory read strobe. rd is activated for every external instruction or data read access. wr / wrl 96 o external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl -mode this pin is activated for low by te data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in register sysc on for mode selection. ready 97 i ready input. when the ready function is enabled, a high level at this pin during an exte rnal memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. an internal pull-up device will hold this pin hi gh when nothing is driving it. ale 98 o address latch enable outpu t. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. ea 99 i external access enable pin. a low level at this pin during and after reset forces the c167cr to begin instru ction execution out of external memory. a high level forces execution out of the internal program memory. ?romless? versions must hav e this pin tied to ?0?. table 2 pin definitions an d functions p-mqfp-144-8 (cont?d) symbol pin no. input outp. function
c167cr c167sr general device information data sheet 14 v3.3, 2005-02 port0 p0l.0-7 p0h.0-7 100- 107 108, 111- 117 io port0 consists of the two 8- bit bidirectional i/o ports p0l and p0h. it is bit-wise programm able for input or output via direction bits. for a pin configur ed as input, the output driver is put into high-impedance state. in case of an external bus co nfiguration, port0 serves as the address (a) and address/dat a (ad) bus in multiplexed bus modes and as the data (d ) bus in demultiplexed bus modes. demultiplexed bus modes: 8-bit data bus: p0h = i/o, p0l = d7 - d0 16-bit data bus: p0h = d15 - d8, p0l = d7 - d0 multiplexed bus modes: 8-bit data bus: p0h = a 15 - a8, p0l = ad7 - ad0 16-bit data bus: p0h = ad15 - ad8, p0l = ad7 - ad0 port1 p1l.0-7 p1h.0-7 p1h.4 p1h.5 p1h.6 p1h.7 118- 125 128- 135 132 133 134 135 io i i i i port1 consists of the two 8-bi t bidirectional i/o ports p1l and p1h. it is bit-wise programm able for input or output via direction bits. for a pin configur ed as input, the output driver is put into high-impedance state. port1 is used as the 16-bit address bus (a) in demultiple xed bus modes and also after switching from a demultiplexe d bus mode to a multiplexed bus mode. the following port1 pi ns also serve for alternate functions: cc24io capcom2: cc24 capture input cc25io capcom2: cc25 capture input cc26io capcom2: cc26 capture input cc27io capcom2: cc27 capture input xtal2 xtal1 137 138 o i xtal2: output of the oscillator amplifier circuit. xtal1: input to the oscillator amplifier and input to the internal clock generator to clock the device from an ex ternal source, drive xtal1, while leaving xtal2 unconne cted. minimum and maximum high/low and rise/fall ti mes specified in the ac characteristics mu st be observed. table 2 pin definitions an d functions p-mqfp-144-8 (cont?d) symbol pin no. input outp. function
c167cr c167sr general device information data sheet 15 v3.3, 2005-02 rstin 140 i/o reset input with schmitt-trigger characteristics. a low level at this pin while the oscillator is running rese ts the c167cr. an internal pull-up resistor per mits power-on reset using only a capacitor connected to v ss . a spike filter suppresses inpu t pulses < 10 ns. input pulses > 100 ns safely pass the filter. the minimum duration for a safe recognition sh ould be 100 ns + 2 cpu clock cycles. in bidirectional reset mode (e nabled by setting bit bdrsten in register syscon) the rstin line is internally pulled low for the duration of the internal reset sequence upon any reset (hw, sw, wdt). see no te below this table. note: to let the reset configuratio n of port0 settle and to let the pll lock a reset duration of ca. 1 ms is recommended. rst out 141 o internal reset indication outpu t. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. rstout remains low until the einit (end of initialization) instruction is executed. nmi 142 i non-maskable interrupt input. a high to low tran sition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power down) instru ction is executed, the nmi pin must be low in order to force the c1 67cr to go into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. v aref 37 ? reference voltage for the a/d converter. v agnd 38 ? reference ground for the a/d converter. table 2 pin definitions an d functions p-mqfp-144-8 (cont?d) symbol pin no. input outp. function
c167cr c167sr general device information data sheet 16 v3.3, 2005-02 note: the following behavioural differences must be observed wh en the bidirectional reset is active: ? bit bdrsten in register syscon cannot be changed after eini t and is cleared automatically after a reset. ? the reset indication flags always indicate a long hardware reset. ? the port0 configuration is treated as if it were a hardware rese t. in particular, the bootstrap loader may be ac tivated when p0l.4 is low. ?pin rstin may only be connected to external re set devices with an open drain output driver. ? a short hardware reset is extended to the duration of the internal reset sequence. v dd 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 ? digital supply voltage: + 5 v during normal ope ration and idle mode. 2.5 v during power down mode. v ss 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 ? digital ground. table 2 pin definitions an d functions p-mqfp-144-8 (cont?d) symbol pin no. input outp. function
c167cr c167sr general device information data sheet 17 v3.3, 2005-02 2.3 pin configuration and definition for p-bga-176-2 the pins 1) of the c167cr are de scribed in detail in table 3 , including all their alternate functions. figure 3 summarizes all pins in a condens ed way, showing their location on the bottom of the package. note: the p-mqfp-144-8 is described in table 2 and figure 2 . figure 3 pin configuration p-bga-176-2 (top view) 1) the external connections of the c1 67cr in p-bga-176-2 are referred to as pins throughout this document, although they are mechanically realized as solder balls. mc_c167crle_pindiagram.vsd a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 1011121314 p5.0 p7.7 p5.4 p5.1 p5.14 p5.15 p5.6 p5.9 p5.7 p5.10 p5.13 p5.11 v ss v dd p2.3 p2.1 p2.4 p2.6 p2.5 p2.7 v ss p2.9 p2.10 p2.12 p2.13 v dd p2.8 p2.11 p2.15 p3.1 v dd p3.2 p3.12 p3.6 p3.13 p4.2 p3.15 p4.6 p4.1 p4.4 p4.3 p4.5 ale p0.1 p0.3 p0.8 p0.2 p0.13 p0.7 p1.3 p0.9 p1.2 p0.10 p1.4 p1.5 p0.15 p0.5 p1.11 p1.13 p0.14 p1.7 p1.9 p1.12 p1.10 p1.14 rst in p1.15 xtal2 nmi xtal1 p6.1 p6.6 p6.0 p6.5 p6.2 p6.3 p8.3 p8.2 p8.0 p8.7 p6.4 p6.7 p8.1 p7.0 p7.6 p8.5 p7.2 p7.5 p7.4 v ss v aref v ss v dd v ss v dd not connected or thermal ground 1 2 3 4 5 6 7 8 9 1011121314 a b c d e f g h j k l m n p p8.4 p5.8 p5.2 p5.5 p7.3 v agnd p5.3 p7.1 v dd rst out v ss p8.6 p5.12 v ss p2.0 p2.2 p1.8 p1.6 v dd p1.1 p1.0 p2.14 v ss v ss rd p0.12 p0.11 v dd ea v ss v dd p3.11 p3.3 p3.0 p3.4 p3.7 p3.8 p3.10 p4.7 wr p0.0 p0.4 p0.6 rea dy v dd p4.0 p3.9 p3.5 owe
c167cr c167sr general device information data sheet 18 v3.3, 2005-02 table 3 pin definitions an d functions p-bga-176-2 symbol pin num. input outp. function p5 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 p5.8 p5.9 p5.10 p5.11 p5.12 p5.13 p5.14 p5.15 a5 d5 a4 c5 b4 a3 c4 d4 b3 c3 d3 c1 d1 d2 e3 e2 i i i i i i i i i i i i i i i i i port 5 is a 16-bit input-only port with schmitt-trigger characteristic. the pins of port 5 also serve as analog input c hannels for the a/d converter, or they serve as timer inputs: an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10, t6eud gpt2 timer t6 ext. up/down ctrl. inp. an11, t5eud gpt2 timer t5 ext. up/down ctrl. inp. an12, t6in gpt2 timer t6 count inp. an13, t5in gpt2 timer t5 count inp. an14, t4eud gpt1 timer t4 ext. up/down ctrl. inp. an15, t2eud gpt1 timer t5 ext. up/down ctrl. inp. p7 p7.0 p7.1 p7.2 p7.3 p7.4 p7.5 p7.6 p7.7 d7 c7 b7 a7 d6 c6 b6 a6 io o o o o i/o i/o i/o i/o port 7 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 7 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 7 is selectable (ttl or special). the following port 7 pins also serve for alternate functions: pout0 pwm channel 0 output pout1 pwm channel 1 output pout2 pwm channel 2 output pout3 pwm channel 3 output cc28io capcom2: cc28 capt ure inp./compare outp. cc29io capcom2: cc29 capt ure inp./compare outp. cc30io capcom2: cc30 capt ure inp./compare outp. cc31io capcom2: cc31 capt ure inp./compare outp.
c167cr c167sr general device information data sheet 19 v3.3, 2005-02 p8 p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 b10 a10 d9 c9 b9 a9 d8 c8 io i/o i/o i/o i/o i/o i/o i/o i/o port 8 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 8 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 8 is selectable (ttl or special). the following port 8 pins also serve for alternate functions: cc16io capcom2: cc16 capt ure inp./compare outp. cc17io capcom2: cc17 capt ure inp./compare outp. cc18io capcom2: cc18 capt ure inp./compare outp. cc19io capcom2: cc19 capt ure inp./compare outp. cc20io capcom2: cc20 capt ure inp./compare outp. cc21io capcom2: cc21 capt ure inp./compare outp. cc22io capcom2: cc22 capt ure inp./compare outp. cc23io capcom2: cc23 capt ure inp./compare outp. p6 p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 a13 b12 d10 c11 a12 b11 c10 a11 io o o o o o i i/o o port 6 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 6 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 6 is selectable (ttl or special). the port 6 pins also serv e for alternate functions: cs0 chip select 0 output cs1 chip select 1 output cs2 chip select 2 output cs3 chip select 3 output cs4 chip select 4 output hold external master hold request input hlda hold acknowledge output (master mode) or input (slave mode) breq bus request output nmi c14 i non-maskable interrupt input. a high to low tran sition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power down) instru ction is executed, the nmi pin must be low in order to force the c1 67cr to go into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. table 3 pin definitions an d functions p-bga-176-2 (cont?d) symbol pin num. input outp. function
c167cr c167sr general device information data sheet 20 v3.3, 2005-02 xtal2 xtal1 d13 c13 o i xtal2: output of the oscillator amplifier circuit. xtal1: input to the oscillator amplifier and input to the internal clock generator. to clock the device from an ex ternal source, drive xtal1, while leaving xtal2 unconne cted. minimum and maximum high/low and rise/fall ti mes specified in the ac characteristics mu st be observed. rst out d12 o internal reset indication outpu t. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. rstout remains low until the einit (end of initialization) instruction is executed. rstin e11 i/o reset input with schmitt-trigger characteristics. a low level at this pin while the oscillator is running rese ts the c167cr. an internal pull-up resistor per mits power-on reset using only a capacitor connected to v ss . a spike filter suppresses inpu t pulses < 10 ns. input pulses > 100 ns safely pass the filter. the minimum duration for a safe recognition sh ould be 100 ns + 2 cpu clock cycles. in bidirectional reset mode (e nabled by setting bit bdrsten in register syscon) the rstin line is internally pulled low for the duration of the internal reset sequence upon any reset (hw, sw, wdt). see no te below this table. note: to let the reset configuratio n of port0 settle and to let the pll lock a reset duration of ca. 1 ms is recommended. table 3 pin definitions an d functions p-bga-176-2 (cont?d) symbol pin num. input outp. function
c167cr c167sr general device information data sheet 21 v3.3, 2005-02 port1 p1l.0-7 p1h.0-3 p1h.4 p1h.5 p1h.6 p1h.7 k13, k14, j13, j14, h11, h12, h13, g11 g13, f11, f12, g14 f13 f14 e14 e13 io i i i i port1 consists of the two 8-bi t bidirectional i/o ports p1l and p1h. it is bit-wise programm able for input or output via direction bits. for a pin configur ed as input, the output driver is put into high-impedance state. port1 is used as the 16-bit address bus (a) in demultiple xed bus modes and also after switching from a demultiplexe d bus mode to a multiplexed bus mode. the following port1 pi ns also serve for alternate functions: cc24io capcom2: cc24 capture input cc25io capcom2: cc25 capture input cc26io capcom2: cc26 capture input cc27io capcom2: cc27 capture input port0 p0l.0-7 p0h.0-7 n10, l9, p11, m10, n11, m11, p12, n12 l10, k11, l12, l14, l13, k12, j11, j12 io port0 consists of the two 8- bit bidirectional i/o ports p0l and p0h. it is bit-wise programm able for input or output via direction bits. for a pin configur ed as input, the output driver is put into high-impedance state. in case of an external bus co nfiguration, port0 serves as the address (a) and address/dat a (ad) bus in multiplexed bus modes and as the data (d ) bus in demultiplexed bus modes. demultiplexed bus modes: 8-bit data bus: p0h = i/o, p0l = d7 - d0 16-bit data bus: p0h = d15 - d8, p0l = d7 - d0 multiplexed bus modes: 8-bit data bus: p0h = a 15 - a8, p0l = ad7 - ad0 16-bit data bus: p0h = ad15 - ad8, p0l = ad7 - ad0 rd l8 o external memory read strobe. rd is activated for every external instruction or data read access. table 3 pin definitions an d functions p-bga-176-2 (cont?d) symbol pin num. input outp. function
c167cr c167sr general device information data sheet 22 v3.3, 2005-02 ea m9 i external access enable pin. a low level at this pin during and after reset forces the c167cr to begin instru ction execution out of external memory. a high level forces execution out of the internal program memory. ?romless? versions must hav e this pin tied to ?0?. wr / wrl n9 o external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl -mode this pin is activated for low by te data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in register sysc on for mode selection. ready p9 i ready input. when the ready function is enabled, a high level at this pin during an exte rnal memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. an internal pull-up device will hold this pin hi gh when nothing is driving it. ale p10 o address latch enable outpu t. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 p6 m6 l6 n7 p7 m7 l7 n8 io o o o o o o i o o o port 4 is an 8-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 4 can be used to output the segment address lines and for serial bus interfaces: a16 least significant segment address line a17 segment address line a18 segment address line a19 segment address line a20 segment address line a21 segment address line, can1_rxd can 1 receive data input a22 segment address line, can1_txd can 1 transmit data output a23 most significant segment address line table 3 pin definitions an d functions p-bga-176-2 (cont?d) symbol pin num. input outp. function
c167cr c167sr general device information data sheet 23 v3.3, 2005-02 owe ( v pp ) n6 i oscillator watchdog e nable. this input enab les the oscillator watchdog when high or disables it when low e.g. for testing purposes. an internal pull-up devi ce holds this input high if nothing is driving it. for normal operation pin owe should be high or not connected. in order to drive pin owe low draw a current of at least 200 a. p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.15 m1 k3 l2 m2 n1 p2 m3 n2 n3 p3 n4 m4 l4 p4 n5 io i o i o i i i i i/o i/o o i/o o o i/o o port 3 is a 15-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 3 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 3 is selectable (ttl or special). the following port 3 pins also serve for alternate functions: t0in capcom1 timer t0 count input t6out gpt2 timer t6 toggle latch output capin gpt2 register caprel capture input t3out gpt1 timer t3 toggle latch output t3eud gpt1 timer t3 extern al up/down control input t4in gpt1 timer t4 count/gate/reload/capture inp. t3in gpt1 timer t3 count/gate input t2in gpt1 timer t2 count/gate/reload/capture inp. mrst ssc master-receive/slave-transmit inp./outp. mtsr ssc master-transmit/slave-receive outp./inp. txd0 asc0 clock/data output (async./sync.) rxd0 asc0 data input (async .) or inp./outp. (sync.) bhe external memory high byte enab le signal, wrh external memory high byte write strobe sclk ssc master clock out put / slave clock input. clkout system clock ou tput (= cpu clock) table 3 pin definitions an d functions p-bga-176-2 (cont?d) symbol pin num. input outp. function
c167cr c167sr general device information data sheet 24 v3.3, 2005-02 p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 f3 f2 f4 g4 g3 g2 g1 h1 h4 j1 j2 j4 j3 k1 k2 l1 io i/o i/o i/o i/o i/o i/o i/o i/o i/o i i/o i i/o i i/o i i/o i i/o i i/o i i/o i i port 2 is a 16-bit bidirectiona l i/o port. it is bit-wise programmable for input or output via direct ion bits. for a pin configured as input, the output driver is put into high- impedance state. port 2 outpu ts can be co nfigured as push/pull or open drain drivers. the input thre shold of port 2 is selectable (ttl or special). the following port 2 pins also serve for alternate functions: cc0io capcom1: cc0 captur e inp./compare output cc1io capcom1: cc1 captur e inp./compare output cc2io capcom1: cc2 captur e inp./compare output cc3io capcom1: cc3 captur e inp./compare output cc4io capcom1: cc4 captur e inp./compare output cc5io capcom1: cc5 captur e inp./compare output cc6io capcom1: cc6 captur e inp./compare output cc7io capcom1: cc7 captur e inp./compare output cc8io capcom1: cc8 captur e inp./compare output, ex0in fast external interrupt 0 input cc9io capcom1: cc9 captur e inp./compare output, ex1in fast external interrupt 1 input cc10io capcom1: cc10 capt ure inp./compare outp., ex2in fast external interrupt 2 input cc11io capcom1: cc11 capt ure inp./compare outp., ex3in fast external interrupt 3 input cc12io capcom1: cc12 capt ure inp./compare outp., ex4in fast external interrupt 4 input cc13io capcom1: cc13 capt ure inp./compare outp., ex5in fast external interrupt 5 input cc14io capcom1: cc14 capt ure inp./compare outp., ex6in fast external interrupt 6 input cc15io capcom1: cc15 capt ure inp./compare outp., ex7in fast external interrupt 7 input, t7in capcom2: timer t7 count input v aref b2 ? reference voltage for the a/d converter. v agnd c2 ? reference ground for the a/d converter. table 3 pin definitions an d functions p-bga-176-2 (cont?d) symbol pin num. input outp. function
c167cr c167sr general device information data sheet 25 v3.3, 2005-02 note: the following behavioural differences must be observed wh en the bidirectional reset is active: ? bit bdrsten in register syscon cannot be changed after eini t and is cleared automatically after a reset. ? the reset indication flags always indicate a long hardware reset. ? the port0 configuration is treated as if it were a hardware rese t. in particular, the bootstrap loader may be ac tivated when p0l.4 is low. ?pin rstin may only be connected to external re set devices with an open drain output driver. ? a short hardware reset is extended to the duration of the internal reset sequence. v dd b8, c12, d14, f1, h3, h14, k4, m5, m12, p8 ? digital supply voltage: + 5 v during normal ope ration and idle mode. 2.5 v during power down mode. v ss a8, d11, e1, e12, g12, h2, l3, l5, l11, m8 ? digital ground. table 3 pin definitions an d functions p-bga-176-2 (cont?d) symbol pin num. input outp. function
c167cr c167sr functional description data sheet 26 v3.3, 2005-02 3 functional description the architecture of the c167cr combi nes advantages of both risc and cisc processors and of advanced peripheral subsystems in a very well-balanced way. in addition the on-chip memory blocks allow the design of compact systems with maximum performance. the following block diagram gi ves an overview of the diff erent on-chip components and of the advanced, high b andwidth internal bus st ructure of the c167cr. note: all time specifications re fer to a cpu clock of 33 mhz (see definition in the ac characteristics section). figure 4 block diagram the program memory, the intern al ram (iram) and the set of generic peripherals are connected to the cpu via sepa rate buses. a fourth bus, the xbus, connects external resources as well as ad ditional on-chip resources, the x-peripherals (see figure 4 ). c166-core cpu port 2 interrupt bus xtal osc / pll wdt 32 16 interrupt controller 16-level priority pec external instr. / data gpt t2 t3 t4 t5 t6 ssc brgen (spi) asc0 brgen (usart) adc 10-bit 16 channels pwm ccom1 t0 t1 ccom2 t7 t8 ebc xbus control external bus control dual port iram internal ram 2 kbyte progmem rom 128/32 kbyte data data 16 16 16 can rev 2.0b active instr. / data port 0 xram 2 kbyte port 6 8 8 port 1 16 16 16 port 5 port 3 15 port 7 8 port 8 8 port 4 16 on-chip xbus (16-bit demux) peripheral data bus 16
c167cr c167sr functional description data sheet 27 v3.3, 2005-02 3.1 memory organization the memory space of the c167c r is configured in a von neumann architecture which means that code memory, data memory, registers and i/o ports are organized within the same linear address space wh ich includes 16 mbytes. the entire memory space can be accessed bytewise or wordwise. particul ar portions of the on-chip memory have additionally been made di rectly bitaddressable. the c167cr incorporates 128/ 32 kbytes (depending on the derivative) of on-chip mask- programmable rom for code or constant data. the lower 32 kbytes of the on-chip rom can be mapped eit her to segment 0 or segment 1. 2 kbytes of on-chip internal ram (iram) ar e provided as a stor age for user defined variables, for the system sta ck, general purpose register banks and even for code. a register bank can consist of up to 16 wordwide (r0 to r1 5) and/or bytewide (rl0, rh0, ?, rl7, rh7) so-called genera l purpose registers (gprs). 1024 bytes (2 512 bytes) of the address space ar e reserved for the special function register areas (sfr space and esfr space) . sfrs are wordwide registers which are used for controlling and monitori ng functions of the differen t on-chip units. unused sfr addresses are reserved for futu re members of the c166 family. 2 kbytes of on-chip extension ram (xram) are provided to store user data, user stacks, or code. the xram is accessed like extern al memory and theref ore cannot be used for the system stack or for register banks an d is not bitaddressabl e. the xram permits 16-bit accesses wi th maximum speed. in order to meet the needs of designs wher e more memory is required than is provided on chip, up to 16 mbytes of external ram and/or rom can be connected to the microcontroller.
c167cr c167sr functional description data sheet 28 v3.3, 2005-02 3.2 external bus controller all of the external memory accesses are perf ormed by a particular on-chip external bus controller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of four different external memory access modes, which are as follows: ? 16-/18-/20-/24-bit addresses, 16-bit data, demultiplexed ? 16-/18-/20-/24-bit addresses, 16-bit data, multiplexed ? 16-/18-/20-/24-bit addresse s, 8-bit data, multiplexed ? 16-/18-/20-/24-bit addresses, 8-bit data, demultiplexed in the demultiplexed bus modes, address es are output on port1 and data is input/output on port0 or p0l, respecti vely. in the multip lexed bus modes both addresses and data use port0 for input/output. important timing characteristics of the ex ternal bus interface (memory cycle time, memory tri-state time, length of ale and read write delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. in addition, up to 4 independent address wi ndows may be defined (via register pairs addrselx / busconx) which co ntrol the access to differ ent resources with different bus characteristics. these address window s are arranged hierarchically where buscon4 overrides buscon 3 and buscon2 overrides buscon1. all accesses to locations not covered by these 4 address windows are controlled by buscon0. up to 5 external cs signals (4 windows plus default) can be generated in order to save external glue logic. the c167cr offers the possibi lity to switch the cs outputs to an unlatched mode. in this mode the internal filter logic is switched off and the cs signals are directly generated from the address. th e unlatched cs mode is enabled by setting cscfg (syscon.6). access to very slow memories or memories with varying access times is supported via a particular ?ready? function. a hold /hlda protocol is available for bus arbitration and al lows to share external resources with other bu s masters. the bus arbitration is enabled by setting bit hlden in register psw. after setting hl den once, pins p6.7 ? p6.5 (breq , hlda , hold ) are automatically controlled by the ebc. in master mode (default after reset) the hlda pin is an output. by setting bit dp6.7 to ?1? the slave mode is selected where pin hlda is switched to input. this allo ws to directly connect the slav e controller to another master controller without glue logic. for applications whic h require less than 16 mbytes of external memory space, this address space can be rest ricted to 1 mbyte, 256 kbyte, or to 64 kbyte. in this case port 4 outputs four, two, or no addre ss lines at all. it outputs all 8 address lines, if an address space of 16 mbytes is used.
c167cr c167sr functional description data sheet 29 v3.3, 2005-02 note: when the on-chip can m odule is to be used th e segment address output on port 4 must be limited to 4 bits (i.e. a19 ? a16) in order to enable the alternate function of the can interface pins. cs lines can be used to increase the total amount of addressabl e external memory.
c167cr c167sr functional description data sheet 30 v3.3, 2005-02 3.3 central processing unit (cpu) the main core of the cpu consists of a 4-st age instruction pipeline , a 16-bit arithmetic and logic unit (alu) and dedi cated sfrs. additional har dware has been spent for a separate multiply and divi de unit, a bit-mask generator and a barrel shifter. based on these hardware pr ovisions, most of the c167 cr?s instructions can be executed in just one mach ine cycle which requires 60 ns at 33 mhz cpu clock. for example, shift and rotate instructions are always processed du ring one machine cycle independent of the number of bits to be shifted. all multiple-cycl e instructions have been optimized so that th ey can be executed very fast as well: branches in 2 cycles, a 16 16 bit multiplication in 5 cycl es and a 32-/16-bit divisi on in 10 cycles. another pipeline optimization, the so-c alled ?jump cache?, allows re ducing the execution time of repeatedly performed ju mps in a loop from 2 cycles to 1 cycle. figure 5 cpu block diagram
c167cr c167sr functional description data sheet 31 v3.3, 2005-02 the cpu has a register context consisting of up to 16 wordwide gp rs at its disposal. these 16 gprs are physically al located within the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu at any time. the number of register banks is only restri cted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 1024 words is prov ided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accesse d by the cpu via the stack pointer (sp) register. two separat e sfrs, stkov and stkun, are implicitly compared against the stack po inter value upon each stack ac cess for the detection of a stack overflow or underflow. the high performance offered by the hardware implementation of th e cpu can efficiently be utilized by a programmer via the highl y efficient c167cr in struction set which includes the following instruction classes: ? arithmetic instructions ? logical instructions ? boolean bit manipula tion instructions ? compare and loop co ntrol instructions ? shift and rotate instructions ? prioritize instruction ? data movement instructions ? system stack instructions ? jump and call instructions ? return instructions ? system control instructions ? miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possibl e operand types are bits, bytes and words. a variety of direc t, indirect or immediate addressing modes are provided to specify the required operands.
c167cr c167sr functional description data sheet 32 v3.3, 2005-02 3.4 interrupt system with an interrupt response time within a r ange from just 5 to 12 cpu clocks (in case of internal program execution), the c167cr is capable of reacting very fast to the occurrence of non-deterministic events. the architecture of the c167cr supports several mechanisms fo r fast and flexible response to service requests that can be generated from various sources internal or external to the microcontrol ler. any of these interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to th e interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec serv ice. a pec service implies a single byte or word data tran sfer between any two memory locations with an additional increment of either th e pec source or the des tination pointer. an in dividual pec transfer counter is implicity decremen ted for each pec service exce pt when performing in the continuous transfer mode. when this counter reaches ze ro, a standard interrupt is performed to the corresponding source related vector loca tion. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the c167cr has 8 pec channels each of which offers such fast interrupt-driven data transfer capabilities. a separate control register wh ich contains an interrupt requ est flag, an interrupt enable flag and an interrupt priority bitfield exists fo r each of the possible interrupt sources. via its related register, each sour ce can be programmed to one of sixteen interrupt priority levels. once having been accepted by the cpu, an interrupt service can only be interrupted by a higher priori tized service request. for the standard interru pt processing, each of the possible interrupt sour ces has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast in terrupt inputs featur e programmable edge detection (rising edge, fall ing edge or both edges). software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. table 4 shows all of the possible c167cr in terrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. note: interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt reque sts by setting the respective interrupt request bit (xir).
c167cr c167sr functional description data sheet 33 v3.3, 2005-02 table 4 c167cr interrupt nodes source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number capcom register 0 cc0ir cc0ie cc0int 00?0040 h 10 h capcom register 1 cc1ir cc1ie cc1int 00?0044 h 11 h capcom register 2 cc2ir cc2ie cc2int 00?0048 h 12 h capcom register 3 cc3ir cc3ie cc3int 00?004c h 13 h capcom register 4 cc4ir cc4ie cc4int 00?0050 h 14 h capcom register 5 cc5ir cc5ie cc5int 00?0054 h 15 h capcom register 6 cc6ir cc6ie cc6int 00?0058 h 16 h capcom register 7 cc7ir cc7ie cc7int 00?005c h 17 h capcom register 8 cc8ir cc8ie cc8int 00?0060 h 18 h capcom register 9 cc9ir cc9ie cc9int 00?0064 h 19 h capcom register 10 cc10 ir cc10ie cc10int 00?0068 h 1a h capcom register 11 cc11 ir cc11ie cc11int 00?006c h 1b h capcom register 12 cc12 ir cc12ie cc12int 00?0070 h 1c h capcom register 13 cc13 ir cc13ie cc13int 00?0074 h 1d h capcom register 14 cc14 ir cc14ie cc14int 00?0078 h 1e h capcom register 15 cc15 ir cc15ie cc15int 00?007c h 1f h capcom register 16 cc16 ir cc16ie cc16int 00?00c0 h 30 h capcom register 17 cc17 ir cc17ie cc17int 00?00c4 h 31 h capcom register 18 cc18 ir cc18ie cc18int 00?00c8 h 32 h capcom register 19 cc19 ir cc19ie cc19int 00?00cc h 33 h capcom register 20 cc20 ir cc20ie cc20int 00?00d0 h 34 h capcom register 21 cc21 ir cc21ie cc21int 00?00d4 h 35 h capcom register 22 cc22 ir cc22ie cc22int 00?00d8 h 36 h capcom register 23 cc23 ir cc23ie cc23int 00?00dc h 37 h capcom register 24 cc24ir cc24ie cc24int 00?00e0 h 38 h capcom register 25 cc25ir cc25ie cc25int 00?00e4 h 39 h capcom register 26 cc26ir cc26ie cc26int 00?00e8 h 3a h capcom register 27 cc27ir cc27ie cc27int 00?00ec h 3b h capcom register 28 cc28ir cc28ie cc28int 00?00e0 h 3c h capcom register 29 cc29 ir cc29ie cc29int 00?0110 h 44 h
c167cr c167sr functional description data sheet 34 v3.3, 2005-02 capcom register 30 cc30 ir cc30ie cc30int 00?0114 h 45 h capcom register 31 cc31 ir cc31ie cc31int 00?0118 h 46 h capcom timer 0 t0ir t0ie t0int 00?0080 h 20 h capcom timer 1 t1ir t1ie t1int 00?0084 h 21 h capcom timer 7 t7ir t7ie t7int 00?00f4 h 3d h capcom timer 8 t8ir t8ie t8int 00?00f8 h 3e h gpt1 timer 2 t2ir t2ie t2int 00?0088 h 22 h gpt1 timer 3 t3ir t3ie t3int 00?008c h 23 h gpt1 timer 4 t4ir t4ie t4int 00?0090 h 24 h gpt2 timer 5 t5ir t5ie t5int 00?0094 h 25 h gpt2 timer 6 t6ir t6ie t6int 00?0098 h 26 h gpt2 caprel reg. crir crie crint 00?009c h 27 h a/d conversion complete adcir adcie adcint 00?00a0 h 28 h a/d overrun error adeir adeie adeint 00?00a4 h 29 h asc0 transmit s0tir s0tie s0tint 00?00a8 h 2a h asc0 transmit buffer s0tbir s0tbie s0tbint 00?011c h 47 h asc0 receive s0rir s0rie s0rint 00?00ac h 2b h asc0 error s0eir s0eie s0eint 00?00b0 h 2c h ssc transmit sctir sctie sctint 00?00b4 h 2d h ssc receive scrir scrie scrint 00?00b8 h 2e h ssc error sceir sceie sceint 00?00bc h 2f h pwm channel 0 ? 3 pwmir pwmie pwmint 00?00fc h 3f h can interface 1 xp0 ir xp0ie xp0int 00?0100 h 40 h unassigned node xp1 ir xp1ie xp1int 00?0104 h 41 h unassigned node xp2 ir xp2ie xp2int 00?0108 h 42 h pll/owd xp3ir xp3ie xp3int 00?010c h 43 h table 4 c167cr interrupt nodes (cont?d) source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number
c167cr c167sr functional description data sheet 35 v3.3, 2005-02 the c167cr also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time , so-called ?hardware traps?. hardware traps cause immediat e non-maskable system reacti on which is similar to a standard interrupt service (b ranching to a dedicated ve ctor table location). the occurrence of a hardware trap is additionally signifi ed by an individual bit in the trap flag register (tfr). except when ano ther higher prioritized trap service is in progress, a hardware trap will interrupt any actual progra m execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. table 5 shows all of the possible e xceptions or error conditions that can arise during run- time: table 5 hardware trap summary exception condition trap flag trap vector vector location trap number trap priority reset functions: ? hardware reset ? software reset ? w-dog timer overflow ? reset reset reset 00?0000 h 00?0000 h 00?0000 h 00 h 00 h 00 h iii iii iii class a hardware traps: ? non-maskable interrupt ? stack overflow ? stack underflow nmi stkof stkuf nmitrap stotrap stutrap 00?0008 h 00?0010 h 00?0018 h 02 h 04 h 06 h ii ii ii class b hardware traps: ? undefined opcode ? protected instruction fault ? illegal word operand access ? illegal instruction access ? illegal external bus access undopc prtflt illopa illina illbus btrap btrap btrap btrap btrap 00?0028 h 00?0028 h 00?0028 h 00?0028 h 00?0028 h 0a h 0a h 0a h 0a h 0a h i i i i i reserved ? ? [2c h - 3c h ][0b h - 0f h ]? software traps ? trap instruction ?? any [00?0000 h - 00?01fc h ] in steps of 4 h any [00 h - 7f h ] current cpu priority
c167cr c167sr functional description data sheet 36 v3.3, 2005-02 3.5 capture/compare (capcom) units the capcom units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 16 tcl. the capcom units are typically used to handle high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digi tal to analog (d/a) conversi on, software timing, or time recording relative to external events. four 16-bit timers (t0/t1, t7/t8) with reload registers prov ide two independent time bases for the capture/co mpare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an over flow/underflow of timer t6 in module gpt2. this provides a wide range of variation for th e timer period and re solution and allows precise adjustments to the appl ication specific requirements . in addition, external count inputs for capcom timers t0 and t7 allow event schedu ling for the capture/compare registers relative to external events. both of the two capture/compare regist er arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, resp ectively), and programmed for capture or compare function. each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin (except for cc24 ? cc27) to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allo cated timer will be latc hed (?captured?) into the capture/compare register in response to an ex ternal event at the port pin which is associated with this register. in addition, a specif ic interrupt request for this capture/compare register is generated. either a po sitive, a negative, or both a positi ve and a negative external signal transition at the pin can be sele cted as the triggering event. the contents of all registers which have been selected fo r one of the five compare mo des are continuously compared with the contents of the allo cated timers. when a match o ccurs between the timer value and the value in a capt ure/compare register, specific ac tions will be taken based on the selected compare mode.
c167cr c167sr functional description data sheet 37 v3.3, 2005-02 table 6 compare modes (capcom) compare modes function mode 0 interrupt- only compare mode; several compare interrupts pe r timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt- only compare mode; only one compare interrupt pe r timer period is generated mode 3 pin set ?1? on ma tch; pin reset ?0? on compare time overflow; only one compare event per ti mer period is generated double register mode two registers operate on one pin; pin toggles on ea ch compare match; several compare events per timer period are possible.
c167cr c167sr functional description data sheet 38 v3.3, 2005-02 figure 6 capcom unit block diagram 3.6 pwm module the pulse width modulation m odule can generate up to four pwm out put signals using edge-aligned or center-ali gned pwm. in addition the pw m module can generate pwm burst signals and single shot outputs. the frequency range of th e pwm signals covers 4 hz to 16.5 mhz (referred to a cpu clock of 33 mhz), depending on the resolution of the pwm output signal. the le vel of the output signals is selectable and the pwm module can generate interrupt requests. mcb02143b mode control (capture or compare) 2 n : 1 f cpu tx input control capcom timer tx ty input control txin interrupt request (tyir) gpt2 timer t6 over/underflow 2 n : 1 f cpu gpt2 timer t6 over/underflow ccxio ccxio 16 capture inputs 16 compare outputs reload reg. txrel capcom timer ty reload reg. tyrel interrupt request (txir) 16 capture/compare interrupt request 16-bit capture/ compare registers x = 0, 7 y = 1, 8 n = 3 ? 10
c167cr c167sr functional description data sheet 39 v3.3, 2005-02 3.7 general purpose timer (gpt) unit the gpt unit represents a very flexible multifunctional ti mer/counter structure which may be used for many different time rela ted tasks such as event timing and counting, pulse width and duty cycle me asurements, pulse generation , or pulse multiplication. the gpt unit incorporates five 16-bit ti mers which are organized in two separate modules, gpt1 and gpt2. each timer in each module may operate independently in a number of different modes, or may be co ncatenated with another timer of the same module. each of the three ti mers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation, which are timer, gated timer, counter, and incremental interface mode. in timer mode, the in put clock for a timer is derived from the cpu clock, divided by a programmable pr escaler, while counter mode allows a timer to be clocked in refere nce to external events. pulse width or duty cycle meas urement is supported in ga ted timer mode, where the operation of a timer is controlled by the ?gat e? level on an external input pin. for these purposes, each timer has one a ssociated port pin (txin) which serves as gate or clock input. the maximum resolu tion of the timers in module gpt1 is 16 tcl. the count direction (up/down ) for each timer is progra mmable by software or may additionally be altered dyna mically by an external sign al on a port pin (txeud) to facilitate e.g. position tracking. in incremental interface mode the gpt1 timers (t2, t3, t4) can be directly connected to the incremental posi tion sensor signals a and b via their respecti ve inputs txin and txeud. direction and count signals are intern ally derived from these two input signals, so the contents of the respec tive timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl) which changes its state on each timer over- flow/underflow. the state of this latch ma y be output on pin t3out e.g. for time out monitoring of external hardware components, or may be used intern ally to clock timers t2 and t4 for measurin g long time periods wi th high resolution. in addition to their basic op erating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the c ontents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is re loaded with the contents of t2 or t4 triggered either by an ex ternal signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are config ured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated with out software intervention.
c167cr c167sr functional description data sheet 40 v3.3, 2005-02 figure 7 block diagram of gpt1 with its maximum resolution of 8 tcl, the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capt ure/reload register (caprel). both timers can be clocked with an input clock wh ich is derived from the cpu clock via a programmable pre scaler or with external si gnals. the count direction (up/down) for each timer is pr ogrammable by software or may additionally be altered dynamically by an external si gnal on a port pin (txeud). concatenati on of the timers is supported via the output toggle latch (t6otl) of timer t6, which change s its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5, and/ or it may be output on pin t6out. the overflows/underflo ws of timer t6 can additi onally be used to clock the capcom timers t0 or t1, and to cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (c apin), and timer t5 may optionally be cleared after the capture procedure. this allows the c167cr to measure absolute time differences or to perform pulse multip lication without so ftware overhead. t3 mode control 2 n : 1 f cpu 2 n : 1 f cpu t2 mode control gpt1 timer t2 reload capture 2 n : 1 f cpu t4 mode control gpt1 timer t4 reload capture gpt1 timer t3 t3otl u/d t2eud t2in t3in t3eud t4in t4eud t3out toggle ff u/d u/d interrupt request interrupt request interrupt request other timers mct02141 n = 3 ? 10
c167cr c167sr functional description data sheet 41 v3.3, 2005-02 the capture trigger (timer t5 to caprel) may also be ge nerated upon transitions of gpt1 timer t3?s inputs t3in and/or t3e ud. this is especially advantageous when t3 operates in incremental interface mode. figure 8 block diagram of gpt2 mux 2 n : 1 f cpu t5 mode control 2 n : 1 f cpu t6 mode control t6otl t5eud t5in t3 capin t6in t6eud t6out u/d u/d interrupt request interrupt request interrupt request other timers clear capture ct3 mcb03999 gpt2 timer t5 gpt2 caprel gpt2 timer t6 n = 2 ? 9
c167cr c167sr functional description data sheet 42 v3.3, 2005-02 3.8 a/d converter for analog signal measurement, a 10-bit a/d converter with 16 multiplexed input channels and a sample an d hold circuit has been integrated on-chip. it uses the method of successive approximation. the sample ti me (for loading the capacitors) and the conversion time is programm able and can so be adjusted to the extern al circuitry. overrun error detection/prot ection is provided for the conversion result register (addat): either an interrupt request will be generated w hen the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case unti l the previous result has been read. for applications which require less than 16 analog input channe ls, the remaining channel inputs can be used as digital input port pins. the a/d converter of the c167 cr supports four different conversion modes. in the standard single channel conv ersion mode, the analog leve l on a specified channel is sampled once and converted to a digital result. in the si ngle channel c ontinuous mode, the analog level on a specif ied channel is re peatedly sampled and converted without software intervention. in th e auto scan mode, the analog levels on a prespecified number of channels are sequentially sa mpled and converted. in the auto scan continuous mode, the number of prespecified channels is repeatedly sampled and converted. in addition, the c onversion of a specific channel can be inserted (injected) into a running sequence without di sturbing this sequence. this is called chann el injection mode. the peripheral event controller (pec) ma y be used to automatically store the conversion results into a ta ble in memory for later eval uation, without requiring the overhead of entering and ex iting interrupt routines for each data transfer. after each reset and also during normal operation the adc automatically performs calibration cycles. this automatic self-calibration cons tantly adjusts the converter to changing operating conditions (e.g. temperature) and comp ensates process variations. these calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the a/d converter. in order to decouple analog inputs from di gital noise and to avoid input trigger noise those pins used for analog in put can be disconnected from the digital io or input stages under software control. this can be selected for each pin se parately via register p5didis (port 5 digital input disable).
c167cr c167sr functional description data sheet 43 v3.3, 2005-02 3.9 serial channels serial communication with other microcontr ollers, processors, terminals or external peripheral components is provided by two serial interfaces wi th different functionality, an asynchronous/synchronous serial channel ( asc0 ) and a high-speed synchronous serial channel ( ssc ). the asc0 is upward compatible with the serial ports of the infineon 8- bit microcontroller families and supports full-duplex asynchronous communi cation at up to 781 kbit/s/1.03 mbit/s and half-duplex synchronous communication at up to 3.1/4.1 mbit/s (@ 25/33 mhz cpu clock). a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmission, recept ion and error handling 4 separate interrupt vectors are provided. in asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a star t bit and terminated by on e or two stop bits. for multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-b it data plus wa ke up bit mode). in synchronous mode, the asc0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the asc0. the asc0 always shifts the lsb first. a loop back option is available for testing purposes. a number of optional hardware error detection cap abilities has been included to increase the reliability of data transfers. a pa rity bit can automatically be generated on transmission or be checked on reception. framing error det ection allows to recognize data frames with missing stop bits. an overrun error will be generated, if the last character received has not been read out of th e receive buffer register at the time the reception of a new ch aracter is complete. the ssc supports full-duplex syn chronous communication at up to 6.25/8.25 mbit/s (@ 25/33 mhz cpu clock). it ma y be configured so it interf aces with serially linked peripheral components. a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmission, recept ion, and error handling three separate interrupt ve ctors are provided. the ssc transmits or receives characters of 2 ? 16 bits leng th synchronously to a shift clock which can be generated by the ssc (mast er mode) or by an ex ternal master (slave mode). the ssc can star t shifting with the lsb or with the msb and allows the selection of shifting and latching clock edges as well as the clock polarity. a number of optional hardware error detection cap abilities has been included to increase the reliability of data transfers. transmit and receive error supervise the correct handling of the data buffer. phase and baudrate error detect inco rrect serial data.
c167cr c167sr functional description data sheet 44 v3.3, 2005-02 3.10 can-module the integrated can-module handles the comple tely autonomous transmission and reception of can frames in a ccordance with the can specific ation v2.0 part b (active), i.e. the on-chip can-module can receive an d transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. the module provides full can functional ity on up to 15 message objects. message object 15 may be configured for basic can functionality. both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in full can mode and also allows to di sregard a number of identifie rs in basic can mode. all message objects can be upda ted independent from the ot her objects and are equipped for the maximum message length of 8 bytes. the bit timing is derived from the xclk and is programmable up to a data rate of 1 mbit/s. the can-module uses two pins of port 4 to inte rface to an external bus transceiver. note: when the can interface is to be used the segment address output on port 4 must be limited to 4 bits, i.e. a19 ? a16. this is necessa ry to enable the alternate function of the can interface pins. 3.11 watchdog timer the watchdog timer represen ts one of the fail-safe mechanisms which have been implemented to prevent the co ntroller from malfunctioning for longer periods of time. the watchdog timer is always enabled afte r a reset of the ch ip, and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. thus, the chip?s start-up proce dure is always monitore d. the software has to be designed to service the watchdog timer be fore it overflows. if , due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardwa re reset and pulls the rstout pin low in order to allow external hardware comp onents to be reset. the watchdog timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. the high byte of the watchdog timer register can be set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the high byte of the watchdog timer is re loaded. thus, time in tervals between 15.5 s and 254 ms can be monitored (@ 33 mhz). the default watchdog timer interval after reset is 3.97 ms (@ 33 mhz).
c167cr c167sr functional description data sheet 45 v3.3, 2005-02 3.12 parallel ports the c167cr provides up to 111 i/o lines which are organi zed into eight input/output ports and one input port. all po rt lines are bit-addressable, and all input/out put lines are individually (bit-wise) progra mmable as inputs or outputs via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the out put drivers of five i/o ports c an be configured (pin by pin) for push/pull operation or open -drain operation via control registers. during the internal reset, all port pins are configured as inputs. the input threshold of port 2, port 3, port 6, port 7, and port 8 is selectable (ttl or cmos like), where the special cmos like i nput threshold re duces noise sensitivity due to the input hysteresis. the i nput threshold may be selected individually for each byte of the respective ports. all port lines have programmable alternate input or output func tions associated with them. all port lines that are not used for thes e alternate functions may be used as general purpose io lines. port0 and port1 may be used as addre ss and data lines wh en accessing external memory, while port 4 outputs the additional segment addr ess bits a23/19/17 ? a16 in systems where segmentation is enabled to access more t han 64 kbytes of memory. port 2, port 8 and port 7 (a nd parts of port1) are associat ed with the capture inputs or compare outputs of the capc om units and/or with the outputs of the pwm module. port 6 provides optional bu s arbitration signals (breq , hlda , hold ) and chip select signals. port 3 includes alternate func tions of timers, serial interf aces, the optional bus control signal bhe /wrh , and the system clock output (clkout). port 5 is used for the analog input channels to the a/d c onverter or timer control signals. the edge characteristics (tra nsition time) of th e c167cr?s port driv ers can be selected via the port driver control register (pdcr). two bits select fast edges (?0?) or reduced edges (?1?) for bus interface pi ns and non-bus pins separately. pdcr.0 = bipec controls port0, port1, port 4, rd , wr , ale, clkout, bhe /wrh . pdcr.4 = nbpec controls port 3, port 8, rstout , rstin (bidir. reset mode).
c167cr c167sr functional description data sheet 46 v3.3, 2005-02 3.13 oscillator watchdog the oscillator watchdog (o wd) monitors the clock sig nal generated by the on-chip oscillator (either with a cryst al or via external clock driv e). for this operation the pll provides a clock signal wh ich is used to supervise transiti ons on the oscillator clock. this pll clock is independe nt from the xtal1 cl ock. when the expected oscillator clock transitions are missing the owd activates the pll unlock / owd interrupt node and supplies the cpu with the pl l clock signal. under these circumstances the pll will oscillate with its basic frequency. in direct drive mode the pll base frequency is used directly ( f cpu = 2 ? 5 mhz). in prescaler mode th e pll base frequency is divided by 2 ( f cpu = 1 ? 2.5 mhz). note: the cpu clock source is only switch ed back to the oscill ator clock after a hardware reset. the oscillator watc hdog can be disabled via hardware by (ext ernally) pulling low pin owe (internal pull-up provides high level if no t connected). in this case (owe = ?0?) the pll remains idle and provides no clock signal, while the cpu clock signal is derived directly from the oscillator clock or via prescaler. also no interrupt request will be generated in case of a missing oscillator clock.
c167cr c167sr functional description data sheet 47 v3.3, 2005-02 3.14 instruction set summary table 7 lists the instructions of th e c167cr in a condensed way. the various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional exec ution of instructio ns, and the opcodes for each instruction can be found in the ?c166 family instruction set manual? . this document also provides a deta iled description of each instruction. table 7 instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply di rect gpr by direct gpr (16 16 bits) 2 div(u) (un)signed divide register mdl by direct gpr (16 / 16 bits) 2 divl(u) (un)signed long divide reg. md by direct gpr (32 / 16 bits) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (wor d/byte operands) 2 / 4 xor(b) bitwise xor, (wor d/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) dire ct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked hi gh/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (b yte) operands 2 / 4 cmpd1/2 compare word data to gp r and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gp r and increment gpr by 1/2 2 / 4
c167cr c167sr functional description data sheet 48 v3.3, 2005-02 prior determine number of sh ift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/rig ht direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) sh ift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word op erand with sign extension 2 / 4 movbz move byte operand to word op erand. with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 j(n)b jump relative if di rect bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bi t if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative su broutine if condition is met 4 calls call absolute subrouti ne in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service rout ine via immediate trap number 2 push, pop push/pop direct word r egister onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segm ent subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 table 7 instruction set summary (cont?d) mnemonic description bytes
c167cr c167sr functional description data sheet 49 v3.3, 2005-02 diswdt disable watchdog timer 4 einit signify end-of-ini tialization on rstout -pin 4 atomic begin atomic sequence 2 extr begin extended re gister sequence 2 extp(r) begin extended page (a nd register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 7 instruction set summary (cont?d) mnemonic description bytes
c167cr c167sr functional description data sheet 50 v3.3, 2005-02 3.15 special function registers overview the following table lists all sfrs which are implemented in the c167cr in alphabetical order. bit-addressable sfrs are marked with the letter ? b ? in column ?name?. sfrs within the extended sfr-space (esfrs) are marked with the letter ? e ? in column ?physical address?. registers within on-chip x-peripherals are marked with the letter ? x ? in column ?physical address?. an sfr can be specified via its individual mnemonic na me. depending on the selected addressing mode, an sfr can be accessed via its physi cal address (using the data page pointers), or via its sh ort 8-bit address (without us ing the data page pointers). note: registers within device specific interface modules (c an) are only present in the corresponding devi ce, of course. table 8 c167cr registers, ordered by name name physical address 8-bit addr. description reset value adcic b ff98 h cc h a/d converter end of conversion interrupt control register 0000 h adcon b ffa0 h d0 h a/d converter control register 0000 h addat fea0 h 50 h a/d converter result register 0000 h addat2 f0a0 h e 50 h a/d converter 2 result register 0000 h addrsel1 fe18 h 0c h address select register 1 0000 h addrsel2 fe1a h 0d h address select register 2 0000 h addrsel3 fe1c h 0e h address select register 3 0000 h addrsel4 fe1e h 0f h address select register 4 0000 h adeic b ff9a h cd h a/d converter overrun error interrupt control register 0000 h buscon0 b ff0c h 86 h bus configuration register 0 0xx0 h buscon1 b ff14 h 8a h bus configuration register 1 0000 h buscon2 b ff16 h 8b h bus configuration register 2 0000 h buscon3 b ff18 h 8c h bus configuration register 3 0000 h buscon4 b ff1a h 8d h bus configuration register 4 0000 h c1btr ef04 h x ? can1 bit timing register uuuu h c1csr ef00 h x ? can1 control / status register xx01 h c1gms ef06 h x ? can1 global mask short ufuu h
c167cr c167sr functional description data sheet 51 v3.3, 2005-02 c1ir ef02 h x ? can1 interrupt register xx h c1lgml ef0a h x ? can1 lower global mask long uuuu h c1lmlm ef0e h x ? can1 lower mask of last message uuuu h c1uar efn2 h x ? can1 upper arbitration register (message n ) uuuu h c1ugml ef08 h x ? can1 upper global mask long uuuu h c1umlm ef0c h x ? can1 upper mask of last message uuuu h caprel fe4a h 25 h gpt2 capture/reload register 0000 h cc0 fe80 h 40 h capcom register 0 0000 h cc0ic b ff78 h bc h capcom register 0 in terrupt ctrl. reg. 0000 h cc1 fe82 h 41 h capcom register 1 0000 h cc10 fe94 h 4a h capcom register 10 0000 h cc10ic b ff8c h c6 h capcom reg. 10 inte rrupt ctrl. reg. 0000 h cc11 fe96 h 4b h capcom register 11 0000 h cc11ic b ff8e h c7 h capcom reg. 11 inte rrupt ctrl. reg. 0000 h cc12 fe98 h 4c h capcom register 12 0000 h cc12ic b ff90 h c8 h capcom reg. 12 inte rrupt ctrl. reg. 0000 h cc13 fe9a h 4d h capcom register 13 0000 h cc13ic b ff92 h c9 h capcom reg. 13 inte rrupt ctrl. reg. 0000 h cc14 fe9c h 4e h capcom register 14 0000 h cc14ic b ff94 h ca h capcom reg. 14 inte rrupt ctrl. reg. 0000 h cc15 fe9e h 4f h capcom register 15 0000 h cc15ic b ff96 h cb h capcom reg. 15 inte rrupt ctrl. reg. 0000 h cc16 fe60 h 30 h capcom register 16 0000 h cc16ic b f160 h e b0 h capcom reg. 16 inte rrupt ctrl. reg. 0000 h cc17 fe62 h 31 h capcom register 17 0000 h cc17ic b f162 h e b1 h capcom reg. 17 inte rrupt ctrl. reg. 0000 h cc18 fe64 h 32 h capcom register 18 0000 h cc18ic b f164 h e b2 h capcom reg. 18 inte rrupt ctrl. reg. 0000 h cc19 fe66 h 33 h capcom register 19 0000 h table 8 c167cr registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c167cr c167sr functional description data sheet 52 v3.3, 2005-02 cc19ic b f166 h e b3 h capcom reg. 19 inte rrupt ctrl. reg. 0000 h cc1ic b ff7a h bd h capcom reg. 1 inte rrupt ctrl. reg. 0000 h cc2 fe84 h 42 h capcom register 2 0000 h cc20 fe68 h 34 h capcom register 20 0000 h cc20ic b f168 h e b4 h capcom reg. 20 inte rrupt ctrl. reg. 0000 h cc21 fe6a h 35 h capcom register 21 0000 h cc21ic b f16a h e b5 h capcom reg. 21 inte rrupt ctrl. reg. 0000 h cc22 fe6c h 36 h capcom register 22 0000 h cc22ic b f16c h e b6 h capcom reg. 22 inte rrupt ctrl. reg. 0000 h cc23 fe6e h 37 h capcom register 23 0000 h cc23ic b f16e h e b7 h capcom reg. 23 inte rrupt ctrl. reg. 0000 h cc24 fe70 h 38 h capcom register 24 0000 h cc24ic b f170 h e b8 h capcom reg. 24 inte rrupt ctrl. reg. 0000 h cc25 fe72 h 39 h capcom register 25 0000 h cc25ic b f172 h e b9 h capcom reg. 25 inte rrupt ctrl. reg. 0000 h cc26 fe74 h 3a h capcom register 26 0000 h cc26ic b f174 h e ba h capcom reg. 26 inte rrupt ctrl. reg. 0000 h cc27 fe76 h 3b h capcom register 27 0000 h cc27ic b f176 h e bb h capcom reg. 27 inte rrupt ctrl. reg. 0000 h cc28 fe78 h 3c h capcom register 28 0000 h cc28ic b f178 h e bc h capcom reg. 28 inte rrupt ctrl. reg. 0000 h cc29 fe7a h 3d h capcom register 29 0000 h cc29ic b f184 h e c2 h capcom reg. 29 inte rrupt ctrl. reg. 0000 h cc2ic b ff7c h be h capcom reg. 2 inte rrupt ctrl. reg. 0000 h cc3 fe86 h 43 h capcom register 3 0000 h cc30 fe7c h 3e h capcom register 30 0000 h cc30ic b f18c h e c6 h capcom reg. 30 inte rrupt ctrl. reg. 0000 h cc31 fe7e h 3f h capcom register 31 0000 h cc31ic b f194 h e ca h capcom reg. 31 inte rrupt ctrl. reg. 0000 h cc3ic b ff7e h bf h capcom reg. 3 inte rrupt ctrl. reg. 0000 h table 8 c167cr registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c167cr c167sr functional description data sheet 53 v3.3, 2005-02 cc4 fe88 h 44 h capcom register 4 0000 h cc4ic b ff80 h c0 h capcom reg. 4 inte rrupt ctrl. reg. 0000 h cc5 fe8a h 45 h capcom register 5 0000 h cc5ic b ff82 h c1 h capcom register 5 in terrupt ctrl. reg. 0000 h cc6 fe8c h 46 h capcom register 6 0000 h cc6ic b ff84 h c2 h capcom reg. 6 inte rrupt ctrl. reg. 0000 h cc7 fe8e h 47 h capcom register 7 0000 h cc7ic b ff86 h c3 h capcom reg. 7 inte rrupt ctrl. reg. 0000 h cc8 fe90 h 48 h capcom register 8 0000 h cc8ic b ff88 h c4 h capcom reg. 8 inte rrupt ctrl. reg. 0000 h cc9 fe92 h 49 h capcom register 9 0000 h cc9ic b ff8a h c5 h capcom reg. 9 inte rrupt ctrl. reg. 0000 h ccm0 b ff52 h a9 h capcom mode contro l register 0 0000 h ccm1 b ff54 h aa h capcom mode contro l register 1 0000 h ccm2 b ff56 h ab h capcom mode contro l register 2 0000 h ccm3 b ff58 h ac h capcom mode contro l register 3 0000 h ccm4 b ff22 h 91 h capcom mode contro l register 4 0000 h ccm5 b ff24 h 92 h capcom mode contro l register 5 0000 h ccm6 b ff26 h 93 h capcom mode contro l register 6 0000 h ccm7 b ff28 h 94 h capcom mode contro l register 7 0000 h cp fe10 h 08 h cpu context pointer register fc00 h cric b ff6a h b5 h gpt2 caprel interrupt ctrl. register 0000 h csp fe08 h 04 h cpu code segment pointer register (read only) 0000 h dp0l b f100 h e 80 h p0l direction control register 00 h dp0h b f102 h e 81 h p0h direction control register 00 h dp1l b f104 h e 82 h p1l direction control register 00 h dp1h b f106 h e 83 h p1h direction control register 00 h dp2 b ffc2 h e1 h port 2 direction control register 0000 h dp3 b ffc6 h e3 h port 3 direction control register 0000 h table 8 c167cr registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c167cr c167sr functional description data sheet 54 v3.3, 2005-02 dp4 b ffca h e5 h port 4 direction control register 00 h dp6 b ffce h e7 h port 6 direction control register 00 h dp7 b ffd2 h e9 h port 7 direction control register 00 h dp8 b ffd6 h eb h port 8 direction control register 00 h dpp0 fe00 h 00 h cpu data page pointer 0 reg. (10 bits) 0000 h dpp1 fe02 h 01 h cpu data page pointer 1 reg. (10 bits) 0001 h dpp2 fe04 h 02 h cpu data page pointer 2 reg. (10 bits) 0002 h dpp3 fe06 h 03 h cpu data page pointer 3 reg. (10 bits) 0003 h exicon b f1c0 h e e0 h external interrupt control register 0000 h mdc b ff0e h 87 h cpu multiply divide control register 0000 h mdh fe0c h 06 h cpu multiply divide reg. ? high word 0000 h mdl fe0e h 07 h cpu multiply divide reg. ? low word 0000 h odp2 b f1c2 h e e1 h port 2 open drain control register 0000 h odp3 b f1c6 h e e3 h port 3 open drain control register 0000 h odp6 b f1ce h e e7 h port 6 open drain control register 00 h odp7 b f1d2 h e e9 h port 7 open drain control register 00 h odp8 b f1d6 h e eb h port 8 open drain control register 00 h ones ff1e h 8f h constant value 1?s regi ster (read only) ffff h p0h b ff02 h 81 h port 0 high reg. (upp er half of port0) 00 h p0l b ff00 h 80 h port 0 low reg. (lower half of port0) 00 h p1h b ff06 h 83 h port 1 high reg. (upp er half of port1) 00 h p1l b ff04 h 82 h port 1 low reg. (lower half of port1) 00 h p2 b ffc0 h e0 h port 2 register 0000 h p3 b ffc4 h e2 h port 3 register 0000 h p4 b ffc8 h e4 h port 4 register (8 bits) 00 h p5 b ffa2 h d1 h port 5 register (read only) xxxx h p5didis b ffa4 h d2 h port 5 digital input disable register 0000 h p6 b ffcc h e6 h port 6 register (8 bits) 00 h p7 b ffd0 h e8 h port 7 register (8 bits) 00 h p8 b ffd4 h ea h port 8 register (8 bits) 00 h table 8 c167cr registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c167cr c167sr functional description data sheet 55 v3.3, 2005-02 pecc0 fec0 h 60 h pec channel 0 control register 0000 h pecc1 fec2 h 61 h pec channel 1 control register 0000 h pecc2 fec4 h 62 h pec channel 2 control register 0000 h pecc3 fec6 h 63 h pec channel 3 control register 0000 h pecc4 fec8 h 64 h pec channel 4 control register 0000 h pecc5 feca h 65 h pec channel 5 control register 0000 h pecc6 fecc h 66 h pec channel 6 control register 0000 h pecc7 fece h 67 h pec channel 7 control register 0000 h picon b f1c4 h e e2 h port input threshold control register 0000 h pdcr f0aa h e 55 h pin driver control register 0000 h pp0 f038 h e 1c h pwm module period register 0 0000 h pp1 f03a h e 1d h pwm module period register 1 0000 h pp2 f03c h e 1e h pwm module period register 2 0000 h pp3 f03e h e 1f h pwm module period register 3 0000 h psw b ff10 h 88 h cpu program status word 0000 h pt0 f030 h e 18 h pwm module up/down counter 0 0000 h pt1 f032 h e 19 h pwm module up/down counter 1 0000 h pt2 f034 h e 1a h pwm module up/down counter 2 0000 h pt3 f036 h e 1b h pwm module up/down counter 3 0000 h pw0 fe30 h 18 h pwm module pulse wi dth register 0 0000 h pw1 fe32 h 19 h pwm module pulse wi dth register 1 0000 h pw2 fe34 h 1a h pwm module pulse wi dth register 2 0000 h pw3 fe36 h 1b h pwm module pulse wi dth register 3 0000 h pwmcon0 b ff30 h 98 h pwm module contro l register 0 0000 h pwmcon1 b ff32 h 99 h pwm module contro l register 1 0000 h pwmic b f17e h e bf h pwm module interrupt control register 0000 h rp0h b f108 h e 84 h system start-up config. reg. (rd. only) xx h s0bg feb4 h 5a h serial channel 0 ba udrate generator reload register 0000 h s0con b ffb0 h d8 h serial channel 0 co ntrol register 0000 h table 8 c167cr registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c167cr c167sr functional description data sheet 56 v3.3, 2005-02 s0eic b ff70 h b8 h serial chan. 0 error in terrupt ctrl. reg. 0000 h s0rbuf feb2 h 59 h serial channel 0 receive buffer reg. (read only) xx h s0ric b ff6e h b7 h serial channel 0 receive interrupt control register 0000 h s0tbic b f19c h e ce h serial channel 0 transmit buffer interrupt control register 0000 h s0tbuf feb0 h 58 h serial channel 0 transmit buffer reg. (write only) 00 h s0tic b ff6c h b6 h serial channel 0 transmit interrupt control register 0000 h sp fe12 h 09 h cpu system stack po inter register fc00 h sscbr f0b4 h e 5a h ssc baudrate register 0000 h ssccon b ffb2 h d9 h ssc control register 0000 h ssceic b ff76 h bb h ssc error interrupt control register 0000 h sscrb f0b2 h e 59 h ssc receive buffer xxxx h sscric b ff74 h ba h ssc receive interrupt control register 0000 h ssctb f0b0 h e 58 h ssc transmit buffer 0000 h ssctic b ff72 h b9 h ssc transmit interrupt control register 0000 h stkov fe14 h 0a h cpu stack overflow pointer register fa00 h stkun fe16 h 0b h cpu stack underflow pointer register fc00 h syscon b ff12 h 89 h cpu system configuration register 1) 0xx0 h t0 fe50 h 28 h capcom timer 0 register 0000 h t01con b ff50 h a8 h capcom timer 0 and ti mer 1 ctrl. reg. 0000 h t0ic b ff9c h ce h capcom timer 0 inte rrupt ctrl. reg. 0000 h t0rel fe54 h 2a h capcom timer 0 re load register 0000 h t1 fe52 h 29 h capcom timer 1 register 0000 h t1ic b ff9e h cf h capcom timer 1 inte rrupt ctrl. reg. 0000 h t1rel fe56 h 2b h capcom timer 1 re load register 0000 h t2 fe40 h 20 h gpt1 timer 2 register 0000 h t2con b ff40 h a0 h gpt1 timer 2 control register 0000 h table 8 c167cr registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c167cr c167sr functional description data sheet 57 v3.3, 2005-02 t2ic b ff60 h b0 h gpt1 timer 2 interrupt control register 0000 h t3 fe42 h 21 h gpt1 timer 3 register 0000 h t3con b ff42 h a1 h gpt1 timer 3 control register 0000 h t3ic b ff62 h b1 h gpt1 timer 3 interrupt control register 0000 h t4 fe44 h 22 h gpt1 timer 4 register 0000 h t4con b ff44 h a2 h gpt1 timer 4 control register 0000 h t4ic b ff64 h b2 h gpt1 timer 4 interrupt control register 0000 h t5 fe46 h 23 h gpt2 timer 5 register 0000 h t5con b ff46 h a3 h gpt2 timer 5 control register 0000 h t5ic b ff66 h b3 h gpt2 timer 5 interrupt control register 0000 h t6 fe48 h 24 h gpt2 timer 6 register 0000 h t6con b ff48 h a4 h gpt2 timer 6 control register 0000 h t6ic b ff68 h b4 h gpt2 timer 6 interrupt control register 0000 h t7 f050 h e 28 h capcom timer 7 register 0000 h t78con b ff20 h 90 h capcom timer 7 an d 8 ctrl. reg. 0000 h t7ic b f17a h e be h capcom timer 7 inte rrupt ctrl. reg. 0000 h t7rel f054 h e 2a h capcom timer 7 re load register 0000 h t8 f052 h e 29 h capcom timer 8 register 0000 h t8ic b f17c h e bf h capcom timer 8 inte rrupt ctrl. reg. 0000 h t8rel f056 h e 2b h capcom timer 8 re load register 0000 h tfr b ffac h d6 h trap flag register 0000 h wdt feae h 57 h watchdog timer regi ster (read only) 0000 h wdtcon ffae h d7 h watchdog timer control register 2) 00xx h xp0ic b f186 h e c3 h can1 module interrupt control register 0000 h xp1ic b f18e h e c7 h unassigned interrupt control register 0000 h xp2ic b f196 h e cb h unassigned interrupt control register 0000 h xp3ic b f19e h e cf h pll/owd interrupt co ntrol register 0000 h zeros b ff1c h 8e h constant value 0?s regi ster (read only) 0000 h 1) the system configuration is selected during reset. 2) the reset value depends on the indicated reset source. table 8 c167cr registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c167cr c167sr electrical parameters data sheet 58 v3.3, 2005-02 4 electrical parameters 4.1 general parameters note: stresses above those listed under ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods ma y affect device reliability. during absolute maximum ra ting overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absol ute maximum ratings. table 9 absolute maximum rating parameters parameter symbol limit values unit notes min. max. storage temperature t st -65 150 c? junction temperature t j -40 150 c under bias voltage on v dd pins with respect to ground ( v ss ) v dd -0.5 6.5 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 v dd + 0.5 v ? input current on any pin during overload condition ?-1010ma? absolute sum of all input currents during overload condition ?? |100|ma? power dissipation p diss ?1.5w?
c167cr c167sr electrical parameters data sheet 59 v3.3, 2005-02 operating conditions the following operating conditions must no t be exceeded in orde r to ensure correct operation of the c167cr. all pa rameters specified in the foll owing sections refer to these operating conditions, un less otherwise noticed. table 10 operating condition parameters parameter symbol limit values unit notes min. max. digital supply voltage v dd 4.5 5.5 v active mode, f cpumax = 33 mhz 2.5 1) 1) output voltages and output currents will be reduced when v dd leaves the range defined for active mode. 5.5 v power down mode digital ground voltage v ss 0 v reference voltage overload current i ov ? 5maper pin 2)3) 2) overload conditions occur if the standard operating condit ions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v dd + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltage must rema in within the specified limits. proper operation is not guaranteed if overload co nditions occur on functional pins like xtal1, rd , wr , etc. 3) not subject to production test - verified by design/characterization. absolute sum of overload currents | i ov |? 50 ma 3) external load capacitance c l ? 50 pf pin drivers in fast edge mode (pdcr.bipec = ?0?) ? 30 pf pin drivers in reduced edge mode (pdcr.bipec = ?1?) 3) ? 100 pf pin drivers in fast edge mode, f cpumax = 25 mhz 4) 4) the increased capacitive load is valid for the 25 mhz-derivatives up to a cpu clock frequency of 25 mhz. under these circumstances the timing parameters as sp ecified in the ?c167cr data sheet 1999-06? are valid. ambient temperature t a 070 c sab-c167cr ? -40 85 c saf-c167cr ? -40 125 c sak-c167cr ?
c167cr c167sr electrical parameters data sheet 60 v3.3, 2005-02 parameter interpretation the parameters listed in the following partly represent the char acteristics of the c167cr and partly its demand s on the system. to aid in interp reting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the c167cr will pr ovide signals with the respec tive timing characteristics. sr ( s ystem r equirement): the external system must prov ide signals with the respecti ve timing characteristics to the c167cr. 4.2 dc parameters table 11 dc characteristics (operating conditions apply) 1) parameter symbol limit va lues unit test condition min. max. input low voltage (ttl, all except xtal1) v il sr -0.5 0.2 v dd - 0.1 v? input low voltage xtal1 v il2 sr -0.5 0.3 v dd v? input low voltage (special threshold) v ils sr -0.5 2.0 v ? input high voltage (ttl, all except rstin and xtal1) v ih sr 0.2 v dd + 0.9 v dd + 0.5 v? input high voltage rstin (when operated as input) v ih1 sr 0.6 v dd v dd + 0.5 v? input high voltage xtal1 v ih2 sr 0.7 v dd v dd + 0.5 v? input high voltage (special threshold) v ihs sr 0.8 v dd - 0.2 v dd + 0.5 v? input hysteresis (special threshold) hys 400 ? mv series resistance = 0 ? output low voltage (port0, port1, port 4, ale, rd , wr , bhe , clkout, rstout , rstin 2) ) v ol cc ? 0.45 v i ol = 2.4 ma output low voltage (all other outputs) v ol1 cc ? 0.45 v i ol = 1.6 ma
c167cr c167sr electrical parameters data sheet 61 v3.3, 2005-02 output high voltage 3) (port0, port1, port 4, ale, rd , wr , bhe , clkout, rstout ) v oh cc 2.4 ? v i oh = -2.4 ma 0.9 v dd ?v i oh = -0.5 ma output high voltage 3) (all other outputs) v oh1 cc 2.4 ? v i oh = -1.6 ma 0.9 v dd ?v i oh = -0.5 ma input leakage current (port 5) i oz1 cc ? 200 na 0 v < v in < v dd input leakage current (all other) 4) i oz2 cc ? 500 na 0.45 v < v in < v dd rstin inactive current 5) i rsth 6) ?-10 a v in = v ih1 rstin active current 5) i rstl 7) -100 ? a v in = v il ready /rd /wr inact. current 8) i rwh 6) ?-40 a v out = 2.4 v ready /rd /wr active current 8) i rwl 7) -500 ? a v out = v olmax ale inactive current 8) i alel 6) ?40 a v out = v olmax ale active current 8) i aleh 7) 500 ? a v out = 2.4 v port 6 inactive current 8) i p6h 6) ?-40 a v out = 2.4 v port 6 active current 8) i p6l 7) -500 ? a v out = v ol1max port0 configuration current 9) i p0h 6) ?-10 a v in = v ihmin i p0l 7) -100 ? a v in = v ilmax xtal1 input current i il cc ? 20 a0 v < v in < v dd pin capacitance 10) (digital i nputs/outputs) c io cc ? 10 pf f = 1 mhz; t a = 25 c 1) keeping signal levels within the levels specified in th is table, ensures operation without overload conditions. for signal levels outside these specifications also refer to the specification of the overload current i ov . 2) valid in bidirectional reset mode only. 3) this specification is not valid for outputs which are sw itched to open drain mode. in this case the respective output will float and the voltage re sults from the external circuitry. 4) this parameter is not valid for pins ready , ale, rd , and wr while the respective pull device is on. 5) these parameters describe the rstin pull-up, which equals a resistance of ca. 50 to 250 k ? . 6) the maximum current may be drawn while the respective signal line remains inactive. 7) the minimum current must be drawn in order to drive the respective signal line active. 8) this specification is valid during reset and during hold-mode or adapt-mode. during hold-mode port 6 pins are only affected, if they are used (configured) for cs output and the open drain function is not enabled. the ready -pull-up is always active, except for power-down mode. table 11 dc characteristics (operating conditions apply) 1) (cont?d) parameter symbol limit va lues unit test condition min. max.
c167cr c167sr electrical parameters data sheet 62 v3.3, 2005-02 9) this specification is valid during reset and during adapt-mode. 10) not subject to production test - verified by design/characterization. table 12 power consumption c167cr (operating conditions apply) parameter symbol limit va lues unit test condition min. max. power supply current (active) with all peripherals active i dd ?15 + 2.5 f cpu ma rstin = v il f cpu in [mhz] 1) 1) the supply current is a function of the operat ing frequency. this dependency is illustrated in figure 9 . these parameters are tested at v ddmax and maximum cpu clock with all outputs disconnected and all inputs at v il or v ih . idle mode supply current i id ?10 + 1.0 f cpu ma rstin = v ih1 f cpu in [mhz] 1) power-down mode supply current i pd ?50 a v dd = v ddmax 2) 2) this parameter is tested including leakage currents. a ll inputs (including pins configured as inputs) at 0 v to 0.1 v or at v dd - 0.1 v to v dd , all outputs (including pins conf igured as outputs) disconnected.
c167cr c167sr electrical parameters data sheet 63 v3.3, 2005-02 figure 9 supply/idle current as a function of operating frequency i [ma] f cpu [mhz] 10 20 30 40 i ddmax i ddtyp i idmax i idtyp 20 40 60 80 100 120 140
c167cr c167sr electrical parameters data sheet 64 v3.3, 2005-02 4.3 analog/digital converter parameters table 13 a/d converter characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. analog reference supply v aref sr 4.0 v dd + 0.1 v 1) 1) tue is tested at v aref = 5.0 v, v agnd = 0 v, v dd = 4.9 v. it is guaranteed by design for all other voltages within the defined voltage range. if the analog reference supply voltage exceeds the power supply voltage by up to 0.2 v (i.e. v aref = v dd + 0.2 v) the maximum tue is increased to 3 lsb. this range is not 100% tested. the specified tue is guaranteed only if the absolute sum of input overload currents on port 5 pins (see i ov specification) does not exceed 10 ma. during the reset calibration sequence the maximum tue may be 4 lsb. analog reference ground v agnd sr v ss - 0.1 v ss + 0.2 v ? analog input voltage range v ain sr v agnd v aref v 2) 2) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. basic clock frequency f bc 0.5 6.25 mhz 3) 3) the limit values for f bc must not be exceeded when selecting the cpu frequency and the adctc setting. conversion time t c cc ? 40 t bc + t s + 2 t cpu ? 4) t cpu = 1/ f cpu 4) this parameter includes the sample time t s , the time for determining the digital result and the time to load the result register with the conversion result. values for the basic clock t bc depend on programming and can be taken from table 14 . this parameter depends on the adc control logic. it is not a real maximum value, but rather a fixum. calibration time after reset t cal cc ? 3328 t bc ? 5) 5) during the reset calibration conversions can be executed (with the current accuracy). the time required for these conversions is added to the total reset calibration time. total unadjusted error tue cc ? 2lsb 1) internal resistance of reference voltage source r aref sr ? t bc / 60 - 0.25 k ? t bc in [ns] 6)7) 6) during the conversion the adc?s ca pacitance must be repeatedly char ged or discharged. the internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. the maximum internal resistance results from the programmed conversion timing. 7) not subject to production test - verified by design/characterization. internal resistance of analog source r asrc sr ? t s / 450 - 0.25 k ? t s in [ns] 7)8) adc input capacitance c ain cc ? 33 pf 7)
c167cr c167sr electrical parameters data sheet 65 v3.3, 2005-02 sample time and conversion time of the c167cr?s a/d converter are programmable. table 14 should be used to ca lculate the above timings. the limit values for f bc must not be exceeded when selecting adctc. converter timing example: 8) during the sample time the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow t he capacitance to reach its final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample time t s depend on programming and can be taken from table 14 . table 14 a/d converter computation table adcon.15|14 (adctc) a/d converter basic clock f bc adcon.13|12 (adstc) sample time t s 00 f cpu / 4 00 t bc 8 01 f cpu / 2 01 t bc 16 10 f cpu / 16 10 t bc 32 11 f cpu / 8 11 t bc 64 assumptions: f cpu = 25 mhz (i.e. t cpu = 40 ns), adctc = ?00?, adstc = ?00? basic clock f bc = f cpu / 4 = 6.25 mhz, i.e. t bc = 160 ns sample time t s = t bc 8 = 1280 ns conversion time t c = t s + 40 t bc + 2 t cpu = (1280 + 6400 + 80) ns = 7.8 s
c167cr c167sr electrical parameters data sheet 66 v3.3, 2005-02 4.4 ac parameters 4.4.1 definition of internal timing the internal operation of the c167cr is controlled by the internal cpu clock f cpu . both edges of the cpu clock can trig ger internal (e.g. pipeline) or external (e.g. bus cycles) operations. the specification of the exte rnal timing (ac characteristi cs) therefore depends on the time between two consecutive edges of the cpu clock, called ?tcl? (see figure 10 ). figure 10 generation mechan isms for the cpu clock the cpu clock signal f cpu can be generated from th e oscillator cl ock signal f osc via different mechanisms. the duration of tcls and their variation (and also the derived external timing) depends on th e used mechanism to generate f cpu . this influence must be regarded when calculati ng the timings for the c167cr. note: the example for pll operat ion shown in the fig. above re fers to a pll factor of 4. the used mechanism to generate the basic cpu clock is selected by bitfield clkcfg in register rp0h.7-5. upon a long hardware reset regi ster rp0h is loaded with th e logic levels present on the mct04338 f osc f cpu phase locked loop operation tcl f osc f cpu direct clock drive f osc f cpu prescaler operation tcl tcl tcl tcl tcl
c167cr c167sr electrical parameters data sheet 67 v3.3, 2005-02 upper half of port0 (p0h), i.e. bitfield clkcfg represen ts the logic levels on pins p0.15-13 (p0h.7-5). table 15 associates the combinations of these three bits with the respective clock generation mode. prescaler operation when prescaler operation is configured (clkcfg = 001 b ) the cpu clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f osc and the high and low time of f cpu (i.e. the duration of an individua l tcl) is defined by the period of the input clock f osc . the timings listed in the ac characterist ics that refer to tcls therefore can be calculated using the period of f osc for any tcl. phase locked loop when pll operation is config ured (via clkcfg) the on -chip phase locked loop is enabled and provides the cpu clock (see table above). the pll multiplies the input frequency by the factor f which is selected via the comb ination of pins p0.15-13 (i.e. f cpu = f osc f ). with every f ?th transition of f osc the pll circuit synch ronizes the cpu clock to the input clock. this synchronization is done smoothly, i.e. the cpu clock frequency does not change abruptly. due to this adaptation to th e input clock the frequency of f cpu is constantly adjusted so it is locked to f osc . the slight variation causes a jitter of f cpu which also effects the duration of individual tcls. table 15 c167cr clock generation modes clkcfg (p0h.7-5) cpu frequency f cpu = f osc f external clock input range 1) 1) the external clock input range refers to a cp u clock range of 10 ? 33 mhz (pll operation). notes 1 1 1 f osc 4 2.5 to 8.25 mhz d efault configuration 1 1 0 f osc 3 3.33 to 11 mhz ? 1 0 1 f osc 2 5 to 16.5 mhz ? 1 0 0 f osc 5 2 to 6.6 mhz ? 0 1 1 f osc 1 1 to 33 mhz direct drive 2) 2) the maximum frequency depends on the duty cycle of the external clock signal. 0 1 0 f osc 1.5 6.66 to 22 mhz ? 0 0 1 f osc / 2 2 to 66 mhz cpu clock via prescaler 0 0 0 f osc 2.5 4 to 13.2 mhz ?
c167cr c167sr electrical parameters data sheet 68 v3.3, 2005-02 the timings listed in the ac characterist ics that refer to tc ls therefore must be calculated using the minimum tcl that is possible under the resp ective circumstances. the actual minimum value for tcl depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the rela tive deviation for periods of more than one tcl is lower than for one single tcl (see formula and figure 11 ). for a period of n tcl the minimum val ue is computed usi ng the corresponding deviation d n : ( n tcl) min = n tcl nom - d n , d n [ns] = (13.3 + n 6.3) / f cpu [mhz], (1) where n = number of consecutive tcls and 1 n 40. so for a period of 3 tcls @ 25 mhz (i.e. n = 3): d 3 = (13.3 + 3 6.3) / 25 = 1.288 ns, and (3tcl) min = 3tcl nom - 1.288 ns = 58.7 ns (@ f cpu = 25 mhz). this is especially important fo r bus cycles using waitstates and e.g. for the operation of timers, serial interfac es, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. note: for all periods longer than 40 tc l the n = 40 value can be used (see figure 11 ). figure 11 approximated maxi mum accumulated pll jitter 1 10 1 5 10 20 d n 20 26.5 ns 30 40 and 10 mhz this approximated formula is valid for 1 n 33 mhz. cpu f 25 mhz 33 mhz 40 mcd04413 n 16 mhz 20 mhz 10 mhz max. jitter
c167cr c167sr electrical parameters data sheet 69 v3.3, 2005-02 direct drive when direct drive is configured (clkcfg = 011 b ) the on-chip phase locked loop is disabled and the cpu clock is directly driven from the internal oscillator with the input clock signal. the frequency of f cpu directly follows the frequency of f osc so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f osc . the timings listed below that refer to tcls therefore must be calculated using the minimum tcl that is possible under the resp ective circumstances. this minimum value can be calculated via the following formula: tcl min = 1/ f osc dc min (dc = duty cycle) (2) for two consecutive tcls the deviat ion caused by the duty cycle of f osc is compensated so the duration of 2tcl is always 1/ f osc . the minimum value tcl min therefore has to be used only once for timi ngs that require an odd number of tcls (1 , 3, ?). timings that require an even number of tcls (2, 4, ?) may use the formula 2tcl = 1/ f osc .
c167cr c167sr electrical parameters data sheet 70 v3.3, 2005-02 4.4.2 external clock drive xtal1 figure 12 external clock drive xtal1 note: if the on-chip oscillator is used toget her with a crystal, the oscillator frequency is limited to a range of 4 mhz to 40 mhz. it is strongly recommended to measure the oscillation al lowance (or margin) in the final target system (layout) to determine the optimum paramete rs for the oscillator operation. please refer to the limits specified by the cryst al supplier. when driven by an external clock signa l it will accept the specified frequency range. operation at lower input frequ encies is possible but is guaranteed by design only (not 100% tested). table 16 external clock drive characteristics (operating conditions apply) parameter symbol direct drive 1:1 prescaler 2:1 pll 1:n unit min. max. min. max. min. max. oscillator period t osc sr 30 ? 15 ? 45 1) 1) the minimum and maximum oscillator periods for pll operation d epend on the sele cted cpu clock generation mode. please see respective table above. 500 1) ns high time 2) 2) the clock input signal must reach the defined levels v il2 and v ih2 . t 1 sr 15 3) 3) the minimum high and low time refers to a duty cycle of 50%. the maximu m operating frequency ( f cpu ) in direct drive mode depends on the dut y cycle of the cl ock input signal. ?5?10?ns low time 2) t 2 sr 15 3) ?5?10?ns rise time 2) t 3 sr?8?5?10ns fall time 2) t 4 sr?8?5?10ns mct02534 3 t 4 t v ih2 v il v dd 0.5 1 t 2 t osc t
c167cr c167sr electrical parameters data sheet 71 v3.3, 2005-02 4.4.3 testing waveforms figure 13 input output waveforms figure 14 float waveforms mca04414 2.4 v 0.45 v 1.8 v 0.8 v 1.8 v 0.8 v test points ac inputs during testing are driven at 2.4 v for a logic ?1? and 0.45 v for a logic ?0?. timing measurements are made at ih v min for a logic ?1? and v il max for a logic ?0?. mca00763 - 0.1 v + 0.1 v + 0.1 v - 0.1 v reference for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded oh v timing points load v v load oh v v ol / v ol level occurs ( i oh ol i / = 20 ma).
c167cr c167sr electrical parameters data sheet 72 v3.3, 2005-02 4.4.4 external bus timing figure 15 clkout signal timing variable memory cycles the bus timing shown below is programmable via the busconx registers. the duration of ale and two types of wait states can be selected. this table summarizes the possible bus cycle durations. table 17 clkout reference signal parameter symbol limits unit min. max. clkout cycle time tc 5 cc 30 1) 1) the clkout cycle time is influenced by the pll jitter. for a single clkout cycle (2 tcl) the deviati on caused by the pll jitter is below 1 ns (for f cpu > 25 mhz). for longer periods the relative deviation decreases (see pll deviation formula). ns clkout high time tc 6 cc 8 ? ns clkout low time tc 7 cc 6 ? ns clkout rise time tc 8 cc ? 4 ns clkout fall time tc 9 cc ? 4 ns table 18 variable memory cycles bus cycle type bus cycle durati on unit 25/33 mhz, 0 waitstates demultiplexed bus cycle with normal ale 4 + 2 (15 - ) + 2 (1 - ) tcl 80 ns/60.6 ns demultiplexed bus cycle with extended ale 6 + 2 (15 - ) + 2 (1 - ) tcl 120 ns/90.9 ns multiplexed bus cycle with normal ale 6 + 2 (15 - ) + 2 (1 - ) tcl 120 ns/90.9 ns multiplexed bus cycle with extended ale 8 + 2 (15 - ) + 2 (1 - ) tcl 160 ns/121.2 ns mct04415 clkout tc 5 tc 6 7 tc 8 tc 9 tc
c167cr c167sr electrical parameters data sheet 73 v3.3, 2005-02 table 19 external bus cycle timing (operating conditions apply) parameter symbol limits unit min. max. output delay from clkout falling edge valid for: address, bhe , early cs , write data out, ale tc 10 cc -2 11 ns output delay from clkout rising edge valid for: latched cs , ale low tc 11 cc -2 6 ns output delay from clkout rising edge valid for: wr low (no rw delay), rd low (no rw delay) tc 12 cc -2 8 ns output delay from clkout falling edge valid for: rd /wr low (with rw delay), rd high (with rw delay) tc 13 cc -2 6 ns input setup time to clkout falling edge valid for: read data in tc 14 sr 14 ? ns input hold time after clkout falling edge valid for: read data in 1) 1) read data are latched with the same (internal) clock e dge that triggers the address change and the rising edge of rd . therefore the read data may be removed immediately after the rising edge of rd . address changes before the end of rd have also no impact on (demultiplexed) read cycles. tc 15 sr 0 ? ns output hold time afte r clkout falling edge valid for: address, bhe , early cs 2) 2) due to comparable propagation delays (at comparable capacitive loads) the address does not change before wr goes high. the minimum output delay ( tc 17min ) is therefore the actual value of tc 19 . tc 17 cc -2 6 ns output hold time after clkout edge 3) valid for: write data out 3) not subject to production test - verified by design/characterization. tc 18 cc -2 ? ns output delay from clkout falling edge valid for: wr high tc 19 cc -2 4 ns turn off delay af ter clkout edge 3) valid for: write data out tc 20 cc ? 7 ns turn on delay after clkout falling edge 3) valid for: write data out tc 21 cc -5 ? ns
c167cr c167sr electrical parameters data sheet 74 v3.3, 2005-02 general notes for the following timing figures these standard notes apply to all subsequent timing figures. additional individual notes are placed at the respective figure. 1. the falling ed ge of signals rd and wr /wrh /wrl /wrcs is controlled by the read/write delay featur e (bit buscon.rwdcx). 2. a bus cycle is extended here , if mctc waitstates are selected or if the ready input is sampled inactive. 3. a bus cycle is extended here, if an mttc waitstate is selected.
c167cr c167sr electrical parameters data sheet 75 v3.3, 2005-02 figure 16 demultiplexed bus, write access d15-d0 wr, wrcs bhe, csxe wrl, wrh, a23-a0 tc 10 mct04416 mctc 1) 2) tc tc 21 10 tc tc 10 tc 12 13 valid tc data out mttc 3) tc 18 20 tc 19 tc 17 tc extended ale csxl tc 10 normal ale clkout tc extended ale cycle 11 10 tc 11 tc tc 10 11 normal ale cycle tc 11
c167cr c167sr electrical parameters data sheet 76 v3.3, 2005-02 figure 17 demultiplexed bus, read access 11 normal ale cycle 11 extended ale cycle 12 rdcs d15-d0 a23-a0, rd, bhe, csxe 10 tc tc tc 10 extended ale csxl clkout normal ale tc tc 10 11 tc 10 tc tc tc 10 tc 1) 2) mctc 13 tc valid mttc 3) data in tc 14 15 tc 13 tc 17 mct04417 tc 11
c167cr c167sr electrical parameters data sheet 77 v3.3, 2005-02 figure 18 multiplexed bus, write access 20 20 mct04418 ad15-ad0 (extended ale) ad15-ad0 (normal ale) wr, wrcs 21 tc 10 tc bhe, csxe wrl, wrh, a23-a16 10 tc low address mttc data out mctc 2) 3) 1) tc 21 tc 10 tc low address tc 10 17 tc 17 tc 10 tc 10 12 tc tc 13 data out tc 18 tc 18 tc tc 19 tc valid tc extended ale csxl 10 tc normal ale clkout normal ale cycle extended ale cycle tc 11 tc tc 11 10 tc 10 tc 11 17
c167cr c167sr electrical parameters data sheet 78 v3.3, 2005-02 figure 19 multiplexed bus, read access 12 11 11 low address extended ale cycle (extended ale) ad15-ad0 (normal ale) ad15-ad0 rdcs rd, a23-a16 bhe, csxe low address tc 21 10 tc 10 tc tc tc 21 10 tc tc 10 extended ale csxl normal ale clkout tc 10 tc 11 tc 10 tc tc tc 10 mctc 2) mttc 3) data in tc tc valid 1) 20 20 17 tc tc 17 tc tc 13 tc tc data in 14 15 tc 14 15 13 tc mct04419 tc 17 normal ale cycle
c167cr c167sr electrical parameters data sheet 79 v3.3, 2005-02 bus cycle control via ready input the duration of an external bus cycle can be c ontrolled by the extern al circuitry via the ready input signal. synchronous ready permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal clkout. asynchronous ready puts no timing constraints on the input signal but incurs one waitstate minimum due to the ad ditional synchroni zation stage. notes (valid also for figure 20 ) 4. cycle as programmed, including mctc waitstates (example shows 0 mctc ws). 5. ready sampled high at this samp ling point generates a ready controlled waitstate, ready sampled low at this sampli ng point terminates the currently running bus cycle. 6. these timings are given for test purposes only, in order to assu re recognition at a specific clock edge. if the asynchronous ready signal does not fu lfill the indicated setup and hold times with respec t to clkout, it must fulfill tc 27 in order to be safely synchronized. proper d eactivation of ready is guaranteed if ready is deactivated in response to the trailing (rising) edge of the corresp onding command (rd or wr ). 7. multiplexed bus modes ha ve a mux waitstate added after a bus cycle, and an additional mttc waitstat e may be inserted here. for a multiplexed bus with mttc waitstate this delay is 2 clkout cycles, for a de multiplexed bus without mttc waitstate this delay is zero. 8. if the next follow ing bus cycle is ready controlled, an active ready signal must be disabled before the first vali d sample point for the next bus cycle. this sample point depends on the mttc waitst ate of the current cycle, and on the mctc waitstates and the ale mode of the next following cycle. if the current cycle uses a multiplexed bus the intrinsic mux waitstate adds another clkout cycle to the ready deactivation time. table 20 ready timing (operating conditions apply) parameter symbol limits unit min. max. input setup time to clkout rising edge valid for: ready input tc 25 cc 12 ? ns input hold time after clkout rising edge valid for: ready input tc 26 cc0?ns asynchronous ready input low time 6) tc 27 cc tc 5 + tc 25 ?ns
c167cr c167sr electrical parameters data sheet 80 v3.3, 2005-02 figure 20 ready timings mct04420 clkout d15-d0 data in 15 14 tc tc running cycle 4) ready ws mux/mttc d15-d0 data out 20 tc tc 18 tc 10 tc 21 (rd, wr) command 1) 12 tc 13 tc tc 13 19 tc / 6) synchronous ready tc 25 26 tc 5) 5) 25 tc 26 tc 26 tc asynchronous ready 25 tc 5) tc 5) 25 tc 26 8) 27 tc the next external bus cycle may start here. 7)
c167cr c167sr electrical parameters data sheet 81 v3.3, 2005-02 external bus arbitration table 21 bus arbitration timing (operating conditions apply) parameter symbol limits unit min. max. hold input setup time to clkout falling edge tc 28 sr 18 ? ns clkout to breq delay tc 29 cc -4 6 ns clkout to hlda delay tc 30 cc -4 6 ns csx release 1) 1) not subject to production test - verified by design/characterization. tc 31 cc 0 10 ns csx drive tc 32 cc -2 6 ns other signals release 1) tc 33 cc 0 10 ns other signals drive 1) tc 34 cc06ns
c167cr c167sr electrical parameters data sheet 82 v3.3, 2005-02 figure 21 external bus arbitr ation, releasing the bus notes 1. the c167cr will complete the currently running bus cycle before granting bus access. 2. this is the first possibility for breq to get active. 3. the cs outputs will be resist ive high (pull-up) after t 33 . latched cs outputs are driven high for 1 tcl before the outp ut drivers are switched off. tc mct04421 cs signals other 33 tc 3) 31 hold hlda breq clkout 28 tc 1) 30 tc 29 tc 2)
c167cr c167sr electrical parameters data sheet 83 v3.3, 2005-02 figure 22 external bus arbitr ation, regaining the bus notes 4. this is the last chance for breq to trigger the indicate d regain-sequence. even if breq is activated earlier, the rega in-sequence is initiated by hold going high. please note that hold may also be deactivated wit hout the c167cr requesting the bus. 5. the next c167cr driv en bus cycle may start here. tc mct04422 cs signals other 34 tc 32 hold hlda breq clkout 28 tc 30 tc 29 tc 4) tc 29 tc 29 5)
c167cr c167sr electrical parameters data sheet 84 v3.3, 2005-02 external xram access if xper-share mode is enabl ed the on-chip xram of the c167cr can be accessed (during hold states) by an external master like an asynchronous sram. figure 23 external access to the xram table 22 xram access timing (operating co nditions apply) 1) 1) the minimum access cycle time is 60 ns. parameter symbol limits unit min. max. address setup time before rd /wr falling edge t 40 sr 4 ? ns address hold time after rd /wr rising edge t 41 sr 0 ? ns data turn on delay after rd falling edge read t 42 cc 1 ? ns data output valid dela y after address latched t 43 cc ? 40 ns data turn off delay after rd rising edge t 44 cc 1 14 ns write data setup time before wr rising edge write t 45 sr 10 ? ns write data hold time after wr rising edge t 46 sr 2 ? ns wr pulse width t 47 sr 20 ? ns wr signal recovery time t 48 sr t 40 ?ns read data 43 t 42 t 44 t mct04423 (rd, wr) write data command address 40 t 45 t 47 t 46 t 48 t 41 t
c167cr c167sr package outlines data sheet 85 v3.3, 2005-02 5 package outlines figure 24 p-mqfp-144-8 (plastic metric quad flat package) does not include plastic or metal protrusion of 0.25 max. per side 4x index marking 1 x 45? 144 a 1 b 35 x 0.65 = 22.75 0.3 0.08 0.65 a-b 144x 28 31.2 1) 0.12 m d d c c a-b a-b 0.2 0.2 d d 0.1 0.25 min. 2.75 max. 2.4 -0.1 0.88 4x h 0.15 h 0.15 +0.08 -0.02 7? max. 1) 28 1) 31.2 gpm05248 you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
c167cr c167sr package outlines data sheet 86 v3.3, 2005-02 figure 25 p-bga-176-2 (plastic ball gr id array package) (0.8) 0.1 0.4 (0.56) 0.5 1.5 0.2 15 4x 13 1 -0.16 +0.14 ?0.5 13 x 1 = 13 a14 1 13 x 1 = 13 2 max. index marking 0.2 (sharp edge) index marking 0.2 15 b 13 1 176x ?0.1 ?0.3 m a c a c b c a1 p1 1 m gpa09430 you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
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